Abstract: Methods and apparatus are provided for processing a signal in a read channel using a selective oversampled analog to digital conversion. The disclosed selective oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain. An analog input signal in a read channel is converted to a digital signal to generate one or more digital samples corresponding to the analog input signal for a given bit interval. The analog input signal is selectively filtered in an analog domain in a first mode and the digital samples are selectively filtered in a digital domain in a second mode. A data detection algorithm is applied to the digital samples to obtain a detected output. The selection of the first mode and the second mode can be, for example, based on channel conditions. The analog to digital conversion can be performed at a baud rate in the first mode and at an oversampled rate in the second mode.

Abstract: Methods and apparatus are provided for processing a signal in a read channel using a selective oversampled analog to digital conversion. The disclosed selective oversampled analog to digital conversion simplifies the analog design by transferring at least a portion of the equalization and/or filtering processes to the digital domain. An analog input signal in a read channel is converted to a digital signal to generate one or more digital samples corresponding to the analog input signal for a given bit interval. The analog input signal is selectively filtered in an analog domain in a first mode and the digital samples are selectively filtered in a digital domain in a second mode. A data detection algorithm is applied to the digital samples to obtain a detected output. The selection of the first mode and the second mode can be, for example, based on channel conditions. The analog to digital conversion can be performed at a baud rate in the first mode and at an oversampled rate in the second mode.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an analog to digital converter, a digital interpolation circuit, a phase error circuit, and a phase adjustment control circuit. The analog to digital converter samples an analog data input at a sampling phase governed at least in part by a coarse control, and provides a series of digital samples. The digital interpolation circuit interpolates between a subset of the series of digital samples based at least in part on a fine control. The phase error circuit calculates a phase error value. The phase adjustment control circuit is operable to determine the coarse control and the fine control based at least in part on the phase error value.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an analog to digital converter, a digital interpolation circuit, a phase error circuit, and a phase adjustment control circuit. The analog to digital converter samples an analog data input at a sampling phase governed at least in part by a coarse control, and provides a series of digital samples. The digital interpolation circuit interpolates between a subset of the series of digital samples based at least in part on a fine control. The phase error circuit calculates a phase error value. The phase adjustment control circuit is operable to determine the coarse control and the fine control based at least in part on the phase error value.

Abstract: A line driver circuit with an output impedance that is set to a value which is based at least in part on the impedance of one or more current sources of the driver circuit. The current source impedance varies depending on the desired output amplitude of the driver circuit. Once the current source impedance is determined, a resistor is selected to be placed in parallel connection with the current source so that the combination of the resistor and the current source impedance will produce a desired output impedance for the driver circuit. Preferably, the driver circuit includes a second current source and second resistor in parallel with each other and a source termination resistor, such that the combination of the current source impedance values and the resistor values produces a desired output impedance for the driver circuit.

Abstract: A signal generator, such as a fractional-N PLL, has, in its feedback signal path, a divider, a phase circuit, and a fractional accumulator that generates control signals for the divider and the phase circuit. The divider control signal controls the divisor value applied by the divider. In one embodiment, a phase selector selects, based on the phase-circuit control signal, one of a plurality of phase-shifted output signals generated by the PLL's main signal path (e.g., by a multi-phase VCO) and the divider generates the feedback signal for the PLL from the selected signal. In another embodiment, the divider generates a divided signal from one of the phase-shifted output signals, and a phase mixer generates, from the divided signal, a plurality of phase-shifted divided signals and selects, based on the phase-circuit signal, one of the phase-shifted divided signals as the PLL's feedback signal.

Abstract: A driver circuit that has a plurality of output elements that are switched on and off in staggered fashion by signals generated by first and second drive chains of a drive chain configuration. The first drive chain comprises “N” delay elements, each of which produces a time delay equal to tDELAY such that the total time delay produced by the first drive chain is equal to (N×tDELAY). The second drive chain comprises N+1 delay elements, “N” of which produce a time delay equal to tDELAY and one of which produces a time delay equal to ½(tDELAY). Therefore, the total time delay produced by the second drive chain is equal to ((N×tDELAY)+(½tDELAY)). The use of the delay element in the second drive that produces the time delay equal to ½(tDELAY) results in smooth transitions in the transition regions where the driver circuit output signal transitions from high to low and from low to high.

Abstract: An auto-detection system and method for a network transceiver that allows the network transceiver to switch from a first rate mode to a second rate mode automatically. In one embodiment, the system includes: (1) an error counter, coupled to a receive input of the network transceiver, that accumulates a count of code violations while the network transceiver is operating in the first rate mode and (2) mode-switching circuitry, coupled to the error counter, that switches the network transceiver to the second rate mode when the count reaches a predetermined value.

Abstract: An arrangement for adjusting a fixed power supply voltage level to a different level that may be required by a connected circuit module comprises a differential amplifier and resistor divider network. A reference voltage is applied to the positive input of the differential amplifier and an internal node voltage within the resistor divider network is fed back as the negative input. The values of the resistors in the network are specifically chosen to provide for the desired voltage level. Each such arrangement of the present invention may then be individually tailored for the particular circumstance.

Abstract: An arrangement for adjusting a fixed power supply voltage level to a different level that may be required by a connected circuit module comprises a differential amplifier and resistor divider network. A reference voltage is applied to the positive input of the differential amplifier and an internal node voltage within the resistor divider network is fed back as the negative input. The values of the resistors in the network are specifically chosen to provide for the desired voltage level. Each such arrangement of the present invention may then be individually tailored for the particular circumstance.

Abstract: A line-driver receives as an input a Manchester-encoded digital data signal, which is then converted into an analog signal by a wave-shaping circuit. The wave-shaping circuit comprises a bank of current sources with a combined output, each current source being actuated by a switch controlled by a switching signal. The current sources are each scaled by a coefficient, and are actuated in a selected sequence during each input data pulse, thereby generating as a combined output a staircase pulse signal with n steps for each input data pulse.

Abstract: A method for tuning an adaptive equalizer in order to receive digital signals from a transmission medium both coarse and fine tuning methods to adaptively equalize a signal received from the transmission medium. The coarse tuning method adjusts an equalizer such that the post equalized signal starts to resemble a known data pattern, such as an MLT3 data pattern. The coarse tuning method monitors and corrects for several things: illegal transitions, over equalization, statistical data pattern anomalies and saturation conditions. Fine tuning methods operate concurrently with the coarse tuning methods and function from the point at which the coarse tuning methods stop being efficient. Additionally, the fine tuning methods hold the waveform locked in. In addition to coarse tuning and fine tuning of the equalizer, the present invention also adjusts gain of the overall signal such that the post equalized signal is always a certain amplitude.

Abstract: In according with the principles of the present invention, a feedback circuit to compensate for process, temperature, and power supply variations in a typical integrated chip is provided. The feedback circuit increases the accuracy and functionality of an integrated chip by generating an output feedback current that is compensated for process, temperature and power supply variations. The feedback circuit comprises a top current mirror circuit, a bottom current mirror circuit, and a sensory circuit connected to the top current mirror circuit. The sensory circuit continuously senses the variations in the process, temperature and power supply and provides the feedback to top current mirror circuit. The top current mirror adjusts its parameters accordingly and therefore an output feedback current is generated which has necessary compensations for the process, temperature and power supply variations.

Abstract: A delay-locked-loop based clock synthesizer for generating, from a reference signal, a clock signal having a frequency different from a frequency of the reference signal includes a delay-locked-loop circuit having a plurality of controllable delay elements serially connected to one another. Each of the delay elements delays the reference signal by an adjustable quantum of time such that the delay elements generate a plurality of delayed signals. A first multiplexer routes one of the delayed signals to a phase detector, which generates a control signal indicative of a difference between a phase of the routed delayed signal and a phase of the reference signal. A feedback loop transfers the control signal from the phase detector to the delay elements, wherein each of the delay elements adjusts, in accordance with the control signal, the quantum of time by which they each delay the reference signal, such that the phase of the reference signal is synchronized with the phase of the routed delayed signal.

Abstract: A master-slave differential comparator having a threshold value. The master section controls the threshold value of the slave section. The slave section is controlled by bias currents therein to matching same in the master section. The bias currents are substantially determined by fixed biases applied to the master section, the difference in biases being substantially equal to the threshold value of the comparator.

Abstract: A variable delay line having a string of "slow" logic inverters and an equal number of "fast" inverters with inputs connected to corresponding "slow" inverter inputs. Transmission gates, coupling the "fast" inverter outputs to corresponding "slow" inverter outputs, vary the amount of current from the "fast" inverters added to the output current of the corresponding "slow" inverters. Maximum delay occurs when substantially no current from the "fast" inverter is added to the "slow" inverter output current and minimum delay occurs when substantially all the current from the "fast" inverter is added to the "slow" inverter output current. The variable delay line may be configured into a variable frequency ring oscillator, useful in phase-locked-loops or the like.

Abstract: A current reference using a switched capacitor to produce a substantially temperature invariant output current. Charge subtracted from a relatively large capacitor by a much smaller switched capacitor at a chosen rate substantially determines the output current of the reference. The output current is proportional to the product of a reference voltage, the capacitance of the switched capacitor and the switching frequency.

Abstract: The loop gain of a phase locked loop is made to be controllably responsive to the transition density of an input data signal. In one embodiment a charge pump, positioned between the phase detector and the loop filter, supplies pulse-amplitude-modulated current pulses to the loop filter, the amplitude of pulses being related to the data transition density.

Abstract: A differential line driver with small common mode shift when going inactive. Two pairs of serially coupled switches diagonally switch when sending data. All switches close when the driver is disabled, the common mode output voltage being established by resistors serially disposed between the pairs of switches and the power source therefore.

Abstract: A peak detector for rapidly following the peak voltage of a pulsed input signal without significant droop between pulses. The peak detector has a master section which selectively controls the droop rate of a slave section. The output of the slave section is the output of the peak detector. The master section droop is determined by a resistor, which may be disconnected therefrom to hold the peak of the input signal.