Patents by Inventor Robert H. Utley

Robert H. Utley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8228797
    Abstract: A system and method for communicating the current congestion state of a destination virtual output queue to a plurality of source queues in order to allow the source queues to adjust their data rates in real time for each class of service is disclosed. The preferred embodiment method comprises tracking the amount of data for one or more classes of service entering and leaving at least one destination queue associated with an output port; determining the amount of available space in the destination queue; creating a message based at least in part on the determined amount of available space; and transmitting the created message to a plurality of source queues at least one of which is providing data to the destination queue.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: July 24, 2012
    Assignee: Fujitsu Limited
    Inventors: Robert H. Utley, Gary F. Chard
  • Patent number: 7782893
    Abstract: An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: August 24, 2010
    Assignee: NextIO Inc.
    Inventors: Christopher J Pettey, Asif Khan, Annette Pagan, Richard E Pekkala, Robert H Utley
  • Patent number: 7590056
    Abstract: A processor includes controller circuitry configurable to determine for a given packet or other protocol data unit (PDU) received by the processor whether the given PDU is a single-cell PDU. If the given PDU is a single-cell PDU, information characterizing the given PDU is stored in first memory circuitry internal to the processor, without utilizing a linked list data structure. If the given PDU is not a single-cell PDU, information characterizing the PDU is stored in second memory circuitry external to the processor, utilizing a linked list data structure. The processor may be configured as a network processor integrated circuit to provide an interface between a network and a switch fabric in a router or switch.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: September 15, 2009
    Assignee: Agere Systems Inc.
    Inventors: Robert A. Corley, Robert H. Utley
  • Patent number: 7290071
    Abstract: A processor includes a plurality of input ports, memory circuitry for storing data blocks associated with protocol data units (PDUs) and received by the processor at the input ports, and controller circuitry coupled to the memory circuitry. The controller circuitry is operative to discard certain ones of the data blocks received at the input ports in an oversubscription condition in which the received data blocks exceed a designated capacity of the processor. A discarded data block indicator is generated for a given one of the input ports if a data block received at the given input port for a particular PDU is discarded. One or more additional data blocks received at the given input port for the particular PDU are discarded based at least in part on the discarded data block indicator. The oversubscription condition may thereby be overcome in a manner which advantageously minimizes the number of received PDUs that are corrupted through discarded data blocks.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: October 30, 2007
    Assignee: Agere Systems Inc.
    Inventor: Robert H. Utley
  • Patent number: 7127547
    Abstract: A processor includes controller circuitry operative to control the storage of a plurality of separate linked list data structures for protocol data units received by the processor. The linked list data structures are stored in memory circuitry associated with the processor, and the memory circuitry is arranged in a plurality of banks. The plurality of banks are configured to store respective ones of the plurality of separate linked list data structures, such that each of the plurality of banks stores a corresponding one of the plurality of separate linked list data structures. The linked list data structures are accessed in an alternating manner that reduces the likelihood of access conflicts between the banks. The processor may be configured as a network processor integrated circuit to provide an interface between a network and a switch fabric in a router or switch.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: October 24, 2006
    Assignee: Agere Systems Inc.
    Inventor: Robert H. Utley
  • Patent number: 6594234
    Abstract: A system and method for maximum utilization of bandwidth of a resource incrementally adjusts in real time the allocated bandwidth per source queue per class of service based at least in part on the current status of a destination virtual output queue fill level. By varying the permissible bandwidth incrementally not only is the available bandwidth utilized optimally but also a desired class of service is maintained.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: July 15, 2003
    Assignee: Fujitsu Network Communications, Inc.
    Inventors: Gary F. Chard, Robert H. Utley