Patents by Inventor Robert J. Baryla

Robert J. Baryla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment
    Patent number: 6970977
    Abstract: In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: November 29, 2005
    Assignee: Bull HN Information Systems Inc.
    Inventors: Wayne R. Buzby, Charles P. Ryan, Robert J. Baryla, William A. Shelly, Lowell D. McCulley
  • Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment
    Publication number: 20040193804
    Abstract: In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Applicant: Bull HN Information Systems Inc.
    Inventors: Wayne R. Buzby, Charles P. Ryan, Robert J. Baryla, William A. Shelly, Lowell D. McCulley
  • Information block transfer management in a multiprocessor computer system employing private caches for individual center processor units and a shared cache
    Patent number: 6006309
    Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller including pairs of half-block operand buffers, each divided into quarter block segments. The operand buffer set is coupled to selectively receive, under control of an input multiplexer, requested information blocks from the CPU bus in quarter-block segments and is further coupled to selectively send, under control of an output multiplexer, received quarter-block segments to the CPU and received full blocks to the cache memory.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: December 21, 1999
    Assignee: Bull HN Information Systems Inc.
    Inventors: William A. Shelly, Minoru Inoshita, Robert J. Baryla
  • Multiprocessor computer system incorporating method and apparatus for dynamically assigning ownership of changeable data
    Patent number: 5963973
    Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: October 5, 1999
    Assignee: Bull HN Information Systems Inc.
    Inventors: Elisabeth Vanhove, Minoru Inoshita, William A. Shelly, Robert J. Baryla
  • Private cache miss and access management in a multiprocessor system with shared memory
    Patent number: 5829029
    Abstract: A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache.
    Type: Grant
    Filed: December 18, 1996
    Date of Patent: October 27, 1998
    Assignee: Bull HN Information Systems Inc.
    Inventors: William A. Shelly, Robert J. Baryla, Minoru Inoshita