Patents by Inventor Robert J. Bayruns
Robert J. Bayruns has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10848106Abstract: An automatic gain control (AGC) transimpedance amplifier (TIA) uses a differential structure with feedback PIN diodes to adjust the loop gain of the amplifier automatically to maintain stability over a wide dynamic range when converting optical power using a photodiode to an electrical signal. A stable DC current derived from the photodiode current sets the voltage gain of the amplifier. The use of ultra-linear long carrier lifetime PIN diodes assures the transimpedance feedback resistance is linear. The AGC function adjusts the gain of the TIA to provide a linear stable differential transresistance controlled by the photodiode current; a linear stable AGC function using current supplied by the photodiode; an improvement of about 10 db of the transresistance dynamic range; and reduces the need for internal and external circuitry needed to provide the same function. The TIA is applicable to CATV optical systems which have very strict linearity requirements.Type: GrantFiled: April 27, 2018Date of Patent: November 24, 2020Assignee: Duet Microelectronics, Inc.Inventor: Robert J. Bayruns
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Patent number: 10784382Abstract: A PIN diode has an anode spaced away from a central region of a top surface of a substrate, such that the anode is in a corner or at a side edge of the top surface. Alternatively, the PIN diode has an anode surrounded by a shield layer. The PIN diode reduces unwanted parasitic capacitance to increase the reverse isolation of RF switches and to reduce the diffusion capacitance to increase the f3dB frequency specification of amplifier circuits. The PIN diode dramatically reduces the values of both parasitic and diffusion capacitances, which enables its application in switches and amplifiers under a wide variety of bias conditions including reverse, low-moderate forward, and large forward-bias; which enables bonding to a much larger metal area than the active electrode, with negligible increase in the parasitic capacitance; and which enables reliable wire-bonding by presenting a highly planar metal surface.Type: GrantFiled: August 13, 2018Date of Patent: September 22, 2020Inventors: Ashok T. Ramu, Robert J. Bayruns, Michel Francois
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Patent number: 10680077Abstract: A heterojunction bipolar transistor (HBT) and methods of fabrication provide a substrate, a base having a first lateral area, an emitter, a sub-collector having a second lateral area, and a collector above the sub-collector, wherein the second lateral area of the sub-collector is less than the first lateral area of the base, which enables the fabrication of HBTs with high linearity, as measured by an improved third order distortion (OIP3) parameter, while maintaining high gain; which enables the fabrication of HBTs with a selectively grown or overgrown collector/sub-collector; and which reduces a capacitance between the base and collector of the HBTs.Type: GrantFiled: June 28, 2018Date of Patent: June 9, 2020Assignee: XG MICROELECTRONICS INC.Inventors: Keun-Yong Ban, Robert J. Bayruns
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Patent number: 10566449Abstract: The present invention is a FET having a p-doped or acceptor-doped layer underneath a FET channel to enable E/D Mode operation. A FET threshold voltage is tunable through a voltage applied to the p-doped layer via a metal contact such as a threshold-control terminal (TCT). The present invention has a dual E/D mode operation of a single FET device, and also a dual E/D mode operation with a single-polarity positive power supply voltage. The FET of the present invention is fabricated to enable dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistors (HEMTs), to enable dual E/D Mode operation by incorporating a p-doped or acceptor doped region underneath the channel, to achieve a tunable threshold voltage by varying the bias voltage on a fourth terminal called the threshold-control terminal (TCT) that contacts the p-doped layer, and to enable Dual E/D-Mode operation of a HEMT with a single-polarity positive power supply voltage.Type: GrantFiled: April 20, 2018Date of Patent: February 18, 2020Assignee: Duet Microelectronics, Inc.Inventors: John Bayruns, Robert J. Bayruns, Ashok T. Ramu
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Publication number: 20200006520Abstract: A heterojunction bipolar transistor (HBT) and methods of fabrication provide a substrate, a base having a first lateral area, an emitter, a sub-collector having a second lateral area, and a collector above the sub-collector, wherein the second lateral area of the sub-collector is less than the first lateral area of the base, which enables the fabrication of HBTs with high linearity, as measured by an improved third order distortion (OIP3) parameter, while maintaining high gain; which enables the fabrication of HBTs with a selectively grown or overgrown collector/sub-collector; and which reduces a capacitance between the base and collector of the HBTs.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: Keun-Yong Ban, Robert J. Bayruns
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Publication number: 20190334482Abstract: An automatic gain control (AGC) transimpedance amplifier (TIA) uses a differential structure with feedback PIN diodes to adjust the loop gain of the amplifier automatically to maintain stability over a wide dynamic range when converting optical power using a photodiode to an electrical signal. A stable DC current derived from the photodiode current sets the voltage gain of the amplifier. The use of ultra-linear long carrier lifetime PIN diodes assures the transimpedance feedback resistance is linear. The AGC function adjusts the gain of the TIA to provide a linear stable differential transresistance controlled by the photodiode current; a linear stable AGC function using current supplied by the photodiode; an improvement of about 10 db of the transresistance dynamic range; and reduces the need for internal and external circuitry needed to provide the same function. The TIA is applicable to CATV optical systems which have very strict linearity requirements.Type: ApplicationFiled: April 27, 2018Publication date: October 31, 2019Applicant: DUET MICROELECTRONICS LLCInventor: Robert J. Bayruns
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Publication number: 20190326425Abstract: The present invention is a FET having a p-doped or acceptor-doped layer underneath a FET channel to enable E/D Mode operation. A FET threshold voltage is tunable through a voltage applied to the p-doped layer via a metal contact such as a threshold-control terminal (TCT). The present invention has a dual E/D mode operation of a single FET device, and also a dual E/D mode operation with a single-polarity positive power supply voltage. The FET of the present invention is fabricated to enable dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistors (HEMTs), to enable dual E/D Mode operation by incorporating a p-doped or acceptor doped region underneath the channel, to achieve a tunable threshold voltage by varying the bias voltage on a fourth terminal called the threshold-control terminal (TCT) that contacts the p-doped layer, and to enable Dual E/D-Mode operation of a HEMT with a single-polarity positive power supply voltage.Type: ApplicationFiled: April 20, 2018Publication date: October 24, 2019Applicant: DUET MICROELECTRONICS LLCInventors: John Bayruns, Robert J. Bayruns, Ashok T. Ramu
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Patent number: 10347738Abstract: Fabrication of a dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistor (HEMT) called a threshold control terminal HEMT (TCT-HEMT) is performed which reduces capacitance between the TCT electrode and the source and drain electrodes of a TCT-HEMT, since such a capacitance may be parasitic, and which fabricates a TCT-HEMT capable of high-frequency operation. A method for fabricating a field-effect transistor (FET) includes: providing a substrate; disposing a back barrier on the substrate to form a base stack; forming a doped layer on the base stack; grow additional layers, including a threshold-control terminal (TCT) access layer; etch a pattern in at least one of the doped layer and the additional layers; and disposing a TCT contact on the TCT access layer.Type: GrantFiled: May 15, 2018Date of Patent: July 9, 2019Assignee: Duet Microelectronics, Inc.Inventors: Ashok T. Ramu, Keun-Yong Ban, John Bayruns, Robert J. Bayruns
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Publication number: 20190109242Abstract: A PIN diode has an anode spaced away from a central region of a top surface of a substrate, such that the anode is in a corner or at a side edge of the top surface. Alternatively, the PIN diode has an anode surrounded by a shield layer. The PIN diode reduces unwanted parasitic capacitance to increase the reverse isolation of RF switches and to reduce the diffusion capacitance to increase the f3dB frequency specification of amplifier circuits. The PIN diode dramatically reduces the values of both parasitic and diffusion capacitances, which enables its application in switches and amplifiers under a wide variety of bias conditions including reverse, low-moderate forward, and large forward-bias; which enables bonding to a much larger metal area than the active electrode, with negligible increase in the parasitic capacitance; and which enables reliable wire-bonding by presenting a highly planar metal surface.Type: ApplicationFiled: August 13, 2018Publication date: April 11, 2019Applicant: DUET MICROELECTRONICS INC.Inventors: Ashok T. Ramu, Robert J. Bayruns, Michel Francois
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Patent number: 8461931Abstract: A Multi-Mode Multi-Band (MMMB) radio frequency (RF) power amplifier circuit operating at multiple frequency bands. The power amplifier circuit comprises a single wideband power amplifier having high output impedance which is configured to be equal to a load impedance of the load connected to the power amplifier circuit. A bias voltage applied to the wideband power amplifier is changed from a first value to a second value to provide a predetermined output power of the wideband power amplifier to the load with the output impedance of wideband power amplifier being equal to the load impedance. The power amplifier circuit also includes an individual harmonic filter for filtering each frequency band independently.Type: GrantFiled: October 28, 2011Date of Patent: June 11, 2013Assignee: Anadigics, Inc.Inventors: Robert J. Bayruns, John VanSaders
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Patent number: 7755422Abstract: This invention controls and modulates switched-mode power amplifiers to enable the production of signals that include amplitude modulation (and possibly, but not necessarily, phase modulation), the average power of which may be controlled over a potentially wide range.Type: GrantFiled: October 10, 2007Date of Patent: July 13, 2010Assignee: Panasonic CorporationInventors: Stephan V. Schell, Wendell B. Sander, Ronald A. Meck, Robert J. Bayruns
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Patent number: 7292105Abstract: This invention controls and modulates switched-mode power amplifiers to enable the production of signals that include amplitude modulation (and possibly, but not necessarily, phase modulation), the average power of which may be controlled over a potentially wide range.Type: GrantFiled: November 21, 2006Date of Patent: November 6, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Stephan V. Schell, Wendell B. Sander, Ronald A. Meck, Robert J. Bayruns
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Patent number: 7212069Abstract: This invention controls and modulates switched-mode power amplifiers to enable the production of signals that include amplitude modulation (and possibly, but not necessarily, phase modulation), the average power of which may be controlled over a potentially wide range.Type: GrantFiled: May 8, 2006Date of Patent: May 1, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Stephan V. Schell, Wendell B. Sander, Ronald A. Meck, Robert J. Bayruns
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Patent number: 7042282Abstract: This invention controls and modulates switched-mode power amplifiers to enable the production of signals that include amplitude modulation (and possibly, but not necessarily, phase modulation), the average power of which may be controlled over a potentially wide range.Type: GrantFiled: January 14, 2005Date of Patent: May 9, 2006Assignee: Tropian, Inc.Inventors: Stephan V. Schell, Wendell B. Sander, Ronald A. Meck, Robert J. Bayruns
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Patent number: 6844776Abstract: This invention controls and modulates switched-mode power amplifiers to enable the production of signals that include amplitude modulation (and possibly, but not necessarily, phase modulation), the average power of which may be controlled over a potentially wide range.Type: GrantFiled: May 7, 2003Date of Patent: January 18, 2005Assignee: Tropian, Inc.Inventors: Stephan V. Schell, Wendell B. Sander, Ronald A. Meck, Robert J. Bayruns
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Patent number: 6734724Abstract: This invention controls and modulates switched-mode power amplifiers to enable the production of signals that include amplitude modulation (and possibly, but not necessarily, phase modulation), the average power of which may be controlled over a potentially wide range.Type: GrantFiled: October 6, 2000Date of Patent: May 11, 2004Assignee: Tropian, Inc.Inventors: Stephan V. Schell, Wendell B. Sander, Ronald A. Meck, Robert J. Bayruns
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Publication number: 20030197556Abstract: This invention controls and modulates switched-mode power amplifiers to enable the production of signals that include amplitude modulation (and possibly, but not necessarily, phase modulation), the average power of which may be controlled over a potentially wide range.Type: ApplicationFiled: May 7, 2003Publication date: October 23, 2003Inventors: Stephan V. Schell, Wendell B. Sander, Ronald A. Meck, Robert J. Bayruns
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Patent number: 6005375Abstract: The present invention provides a power amplifier operating with a single power supply. The amplifier includes at least one depletion-mode FET for amplifying an ac signal and a negative voltage generator for providing a bias to the FET. Preferably the amplifier further includes a negative voltage regulator to provide a regulated bias to bias the FET for a class A, AB or B operation. The negative generator includes a multivibrator for producing two clock signals and a charge pump which receives the clock signals and produces a negative voltage. Advantageously the negative voltage is provided as a low reference potential to the multivibrator so that the clock signals it produced include a negative voltage period, which enables the charge pump to operate in a power efficient manner.Type: GrantFiled: May 5, 1998Date of Patent: December 21, 1999Inventors: John van Saders, Robert J. Bayruns
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Patent number: 5952860Abstract: The present invention provides a power amplifier operating with a single power supply. The amplifier includes at least one depletion-mode FET for amplifying an ac signal and a negative voltage generator for providing a bias to the FET. Preferably the amplifier further includes a negative voltage regulator to provide a regulated bias to bias the FET for a class A, AB or B operation. The negative generator includes a multivibrator for producing two clock signals and a charge pump which receives the clock signals and produces a negative voltage. Advantageously the negative voltage is provided as a low reference potential to the multivibrator so that the clock signals it produced include a negative voltage period, which enables the charge pump to operate in a power efficient manner.Type: GrantFiled: May 5, 1998Date of Patent: September 14, 1999Assignee: Anadigics, Inc.Inventors: John van Saders, Robert J. Bayruns
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Patent number: 5892400Abstract: The present invention provides a power amplifier operating with a single power supply. The amplifier includes at least one depletion-mode FET for amplifying an ac signal and a negative voltage generator for providing a bias to the FET. Preferably the amplifier further includes a negative voltage regulator to provide a regulated bias to bias the FET for a class A, AB or B operation. The negative generator includes a multivibrator for producing two clock signals and a charge pump which receives the clock signals and produces a negative voltage. Advantageously the negative voltage is provided as a low reference potential to the multivibrator so that the clock signals it produced include a negative voltage period, which enables the charge pump to operate in a power efficient manner.Type: GrantFiled: December 12, 1996Date of Patent: April 6, 1999Assignee: Anadigics, Inc.Inventors: John van Saders, Robert J. Bayruns