Abstract: The present disclosure relates to minimizing the execution time of compute workloads in a distributed computing system. An example method generally includes receiving, from each of a plurality of server clusters, an estimated completion time and cost information predicted to be consumed in processing the compute workload. A workload manager compares the received estimates to a completion time and threshold cost criteria. Upon determining that the estimated completion time and cost information from any of the plurality of server clusters does not satisfy the completion time and threshold cost criteria, the workload manager partitions the compute workload into a plurality of segments, requests estimated completion time and cost information from the plurality of server clusters for each of the plurality of segments, and selects a cluster to process each segment of the compute workload based on the estimated completion time and cost reported for each segment.

Abstract: The present disclosure relates to minimizing the execution time of compute workloads in a distributed computing system. An example method generally includes receiving, from each of a plurality of server clusters, an estimated completion time and cost information predicted to be consumed in processing the compute workload. A workload manager compares the received estimates to a completion time and threshold cost criteria. Upon determining that the estimated completion time and cost information from any of the plurality of server clusters does not satisfy the completion time and threshold cost criteria, the workload manager partitions the compute workload into a plurality of segments, requests estimated completion time and cost information from the plurality of server clusters for each of the plurality of segments, and selects a cluster to process each segment of the compute workload based on the estimated completion time and cost reported for each segment.

Abstract: A computing system includes at least one processor and at least one module operable by the at least one processor to calculate a tail of a first dataset by determining elements of the first dataset that fall outside of a specified percentile, and determine locations of the first dataset at which elements of the first dataset that fall outside of the specified percentile are located. The at least one module may be operable to calculate a tail of a second dataset by populating a data structure with elements of the second dataset that correspond to the locations of the first dataset, and determining, using the data structure, elements of the second dataset that fall outside of the specified percentile. The at least one module may be operable to output an indication of at least one of the tail of the first dataset or the tail of the second dataset.

Abstract: A computing system includes at least one processor and at least one module operable by the at least one processor to calculate a tail of a first dataset by determining elements of the first dataset that fall outside of a specified percentile, and determine locations of the first dataset at which elements of the first dataset that fall outside of the specified percentile are located. The at least one module may be operable to calculate a tail of a second dataset by populating a data structure with elements of the second dataset that correspond to the locations of the first dataset, and determining, using the data structure, elements of the second dataset that fall outside of the specified percentile. The at least one module may be operable to output an indication of at least one of the tail of the first dataset or the tail of the second dataset.

Abstract: A computing system includes at least one processor and at least one module operable by the at least one processor to calculate a tail of a first dataset by determining elements of the first dataset that fall outside of a specified percentile, and determine locations of the first dataset at which elements of the first dataset that fall outside of the specified percentile are located. The at least one module may be operable to calculate a tail of a second dataset by populating a data structure with elements of the second dataset that correspond to the locations of the first dataset, and determining, using the data structure, elements of the second dataset that fall outside of the specified percentile. The at least one module may be operable to output an indication of at least one of the tail of the first dataset or the tail of the second dataset.

Abstract: A computing system includes at least one processor and at least one module operable by the at least one processor to calculate a tail of a first dataset by determining elements of the first dataset that fall outside of a specified percentile, and determine locations of the first dataset at which elements of the first dataset that fall outside of the specified percentile are located. The at least one module may be operable to calculate a tail of a second dataset by populating a data structure with elements of the second dataset that correspond to the locations of the first dataset, and determining, using the data structure, elements of the second dataset that fall outside of the specified percentile. The at least one module may be operable to output an indication of at least one of the tail of the first dataset or the tail of the second dataset.

Abstract: In a multiprocessor data processing system having a distributed shared memory system, a memory transaction that is a rewind-only transaction (ROT) and that includes one or more transactional memory access instructions and a transactional abort instruction is executed. In response to execution of the one or more transactional memory access instructions, one or more memory accesses to the distributed shared memory system indicated by the one or more transactional memory access instructions are performed. In response to execution of the transactional abort instruction, execution results of the one or more transaction memory access instructions are discarded and control is passed to a fail handler.

Abstract: As disclosed herein a method, executed by a computer, for conducting non-recursive cascading reduction includes receiving a collection of floating point values, using a binary representation of an index corresponding to a value being processed to determine a reduction depth for elements on a stack to be accumulated, and according to the reduction depth, iteratively conducting a reduction operation on the current value and one or more values on the stack. In addition to accumulation, the reduction operation may include transforming the value with a corresponding function. The method may also include using a SIMD processing environment to further increase the performance of the method. The method provides results with both high performance and accuracy. A computer system and computer program product corresponding to the method are also disclosed herein.

Abstract: As disclosed herein a method, executed by a computer, for conducting non-recursive cascading reduction includes receiving a collection of floating point values, using a binary representation of an index corresponding to a value being processed to determine a reduction depth for elements on a stack to be accumulated, and according to the reduction depth, iteratively conducting a reduction operation on the current value and one or more values on the stack. In addition to accumulation, the reduction operation may include transforming the value with a corresponding function. The method may also include using a SIMD processing environment to further increase the performance of the method. The method provides results with both high performance and accuracy. A computer system and computer program product corresponding to the method are also disclosed herein.

Abstract: Techniques are disclosed for computing a real-time credit risk score. In one example, the method comprises at least one processor generating a computation graph comprising static computation nodes, dynamic computation nodes, and computation edges. The computation graph is a tree. Before receiving the real-time trade, the processor determines a pipeline kernel in the computation graph and computes the respective static information in the pipeline kernel. After computing the static information, the processor receives the real-time trade. The real-time trade is associated with a current exchange of assets for which a real-time credit risk score may be determined and comprises real-time information for use in computing the real-time credit risk score. The processor computes, based on the real-time trade and the computed static information, the dynamic information in the pipeline kernel and computes, based on the computed dynamic information, the real-time credit risk score.

Abstract: Techniques are disclosed for computing a real-time credit risk score. In one example, the method comprises at least one processor generating a computation graph comprising static computation nodes, dynamic computation nodes, and computation edges. The computation graph is a tree. Before receiving the real-time trade, the processor determines a pipeline kernel in the computation graph and computes the respective static information in the pipeline kernel. After computing the static information, the processor receives the real-time trade. The real-time trade is associated with a current exchange of assets for which a real-time credit risk score may be determined and comprises real-time information for use in computing the real-time credit risk score. The processor computes, based on the real-time trade and the computed static information, the dynamic information in the pipeline kernel and computes, based on the computed dynamic information, the real-time credit risk score.

Abstract: A method for recording and profiling information of a plurality of aborted transactions from a plurality of transactions is executed by processor core with a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.

Abstract: A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.

Abstract: Embodiments of the present invention provide a method, system and computer program product for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management. In an embodiment of the invention, a method for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management can include setting different hardware registers with different priority values for correspondingly different transactions in a transactional memory system configured for transactional memory management according to respective priority values specified by priority assignment logic in external software support for the system. The method also can include detecting a conflict amongst the transactions in the system. Finally, the method can include applying conflict arbitration within the system based upon the priority values specified by the priority assignment logic in the external software support for the system.

Abstract: A method for executing a transaction in a data processing system initiates the transaction by a transactional-memory system coupled to that memory component. The method includes initiating the transaction by a transactional-memory system that is part of a memory component of the data processing system. The transaction includes instructions for comparing multiple parameters, and aborting the transaction by the transactional-memory system based upon a comparison of the multiple parameters.

Abstract: Generating decode time instruction optimization (DTIO) object code that enables a DTIO enabled processor to optimize execution of DTIO instructions. A code sequence configured to facilitate DTIO in a DTIO enabled processor is identified by a computer. The code sequence includes an internal representation (IR) of a first instruction and an IR of a second instruction. The second instruction is dependent on the first instruction. A schedule associated with at least one of the IR of the first instruction and the IR of the second instruction is modified. The modifying includes generating a modified schedule that is configured to place the first instruction next to the second instruction. An object file is generated based on the modified schedule. The object file includes the first instruction placed next to the second instruction. The object file is emitted.

Abstract: A method for executing a transaction in a data processing system initiates the transaction by a transactional-memory system coupled to that memory component. The method includes initiating the transaction by a transactional-memory system that is part of a memory component of the data processing system. The transaction includes instructions for comparing multiple parameters, and aborting the transaction by the transactional-memory system based upon a comparison of the multiple parameters.

Abstract: A method for recording and profiling information of a plurality of aborted transactions from a plurality of transactions is executed by processor core with a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.

Abstract: A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.

Abstract: In a multiprocessor data processing system having a distributed shared memory system, a memory transaction that is a rewind-only transaction (ROT) and that includes one or more transactional memory access instructions and a transactional abort instruction is executed. In response to execution of the one or more transactional memory access instructions, one or more memory accesses to the distributed shared memory system indicated by the one or more transactional memory access instructions are performed. In response to execution of the transactional abort instruction, execution results of the one or more transaction memory access instructions are discarded and control is passed to a fail handler.