Abstract: A system, including: a first current mirror having a first current, formed of multiple devices disposed on a substrate, where, when a stress is present, a behavior of a device of the multiple devices forming the first current mirror depends on a direction in which the device of the multiple devices forming the first current mirror is disposed on the substrate; a second current mirror having a second current, formed of multiple devices disposed on the substrate, where, when the stress is present, a behavior of a device of the multiple devices forming the second current mirror depends on a direction in which the device of the multiple devices forming the second current mirror is disposed on the substrate; and a device for measuring a ratio of a difference between the first current and the second current to a sum of the first current and the second current.

Abstract: A system, including: a first current mirror having a first current, formed of multiple devices disposed on a substrate, where, when a stress is present, a behavior of a device of the multiple devices forming the first current mirror depends on a direction in which the device of the multiple devices forming the first current mirror is disposed on the substrate; a second current mirror having a second current, formed of multiple devices disposed on the substrate, where, when the stress is present, a behavior of a device of the multiple devices forming the second current mirror depends on a direction in which the device of the multiple devices forming the second current mirror is disposed on the substrate; and a device for measuring a ratio of a difference between the first current and the second current to a sum of the first current and the second current.

Abstract: A device is described, including a first diffusion region having a first terminal, a second diffusion region having a second terminal, and a channel region disposed between the first diffusion region and the second diffusion region. Further, the first terminal and the second terminal are offset to enable a non-Manhattan current flow. A system is also described, including the previously described device and a second transistor. The pathway for the flow of the majority of the current carriers in the device defines a first direction. The second transistor also has at least two terminals, and a pathway for a majority of current carriers between the two terminals defines a second direction. The angle between the first direction and the second direction is nonzero and acute.

Abstract: A computer system includes a substrate on which a first current mirror and a second current mirror are disposed. When a stress is present, a behavior, e.g., carrier mobility, of at least one of the devices in each of the first current mirror and the second current mirror is dependent on a direction in which that device is disposed on the substrate. Further, one of the devices in the first current mirror is disposed in a non-parallel orientation with respect to one of the devices in the second current mirror.

Abstract: The clock signal is the dominant source of electromagnetic interference (EMI) for many digital electronic devices. EMI generated by these electronic devices must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. The present invention seeks to reduce EMI emissions by phase-modulating the clock signal using tunable delay lines. Phase modulation causes a spreading of the energy spectrum of the clock signal thereby reducing EMI emissions. In addition, the present invention is capable of generating a wide energy spectrum in a short time interval. Furthermore, the present invention can be similarly applied to other signals which exhibit a periodic or timing nature due to a correlation with the clock signal.

Abstract: One embodiment of the present invention provides a system for detecting light which is incident to a first semiconductor die. During operation, the system receives light at a photo-detector on the first semiconductor die, wherein associated circuitry converts the received light into a current. In doing so, the associated circuitry biases a gate voltage of an integrating transistor to be close to a threshold voltage of the integrating transistor, and applies the current from the photo-detector to the gate of the integrating transistor so that the current causes a charge to collect at the gate of the integrating transistor. This charge builds up and causes the integrating transistor to switch, thereby indicating that light has been received by the photo-detector.

Abstract: An analog-to-digital converter generates and adjusts a digital signal based on a delay caused by an analog signal. The analog signal controls a delay of a first delay chain, and the digital signal controls a delay of a second delay chain. Dependent on a comparison of an output of the first delay chain and an output of the second delay chain, circuitry of the analog-to-digital converter adjusts the digital signal.

Abstract: A method and apparatus for generating a reference signal involves (i) generating a CTAT voltage and a PTAT voltage, (ii) generating a first digital signal and a second digital signal having an amplified difference dependent on a difference between the CTAT voltage and the PTAT voltage, and (iii) dependent on the first digital signal and the second digital signal, adding or subtracting charge from the reference signal, where the reference signals controls the conductivity of devices that drive current through the devices that are used to generate the CTAT and PTAT voltages.

Abstract: A system is presented for latching and amplifying a capacitively coupled inter-chip communication signal that operates by receiving an input signal on a capacitive receiver pad and feeding the input signal through an inverter to produce an output signal. The output signal is fed back through a weakened inverter to produce a feedback signal that is fed into an input of the inverter to form a latch for the input signal. The weakened inverter is biased to produce a feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL. VH is set slightly higher than the switching threshold of the inverter, and VL is set slightly lower than the switching threshold. This feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal.

Abstract: One embodiment of the present invention provides a system that amplifies capacitively coupled inter-chip communication signals. During operation, the system transmits a signal through a capacitive transmitter pad and receives a corresponding input signal through a capacitive receiver pad. The system amplifies the input signal by feeding it through a number of cascaded CMOS inverters operating from ever-increasing power supply voltages from the first to the last inverter.

Abstract: One embodiment of the present invention provides a system that facilitates aligning a first semiconductor die with a second semiconductor die, wherein the first semiconductor die and the second semiconductor die are arranged active face to active face. Note that the active face contains circuitry for communicating between semiconductor dies. The system starts by generating light on an active face of the first semiconductor die. The system then collimates the light within the active face of the first semiconductor die to form a first beam of light which is projected onto the second semiconductor die. Next, the system receives the first beam of light on an active face of the second semiconductor die and determines a position of the first beam of light on the active face of the second semiconductor die. Finally, the system determines an alignment of the second semiconductor die relative to the first semiconductor die based on the determined position of the first beam of light.

Abstract: The present invention relates to an integrated circuit device and method of adjusting capacitance of a node of an integrated circuit In one embodiment, the device comprises a first digital input, a first parasitic capacitance block, a first output, a second digital input, a second parasitic capacitance block and a second output. The first parasitic capacitance block includes an inverter, a variable capacitance element, and a wire capacitance element. The first parasitic capacitance block has a capacitance that is a function of the first digital input. The first output is responsive to the first parasitic capacitance block, and the second output is responsive to the second parasitic capacitance block.

Abstract: One embodiment of the present invention provides a system that facilitates aligning a first semiconductor die with a second semiconductor die, wherein the first semiconductor die and the second semiconductor die are arranged active face to active face. Note that the active face contains circuitry for communicating between semiconductor dies. The system starts by generating light on an active face of the first semiconductor die. The system then collimates the light within the active face of the first semiconductor die to form a first beam of light which is projected onto the second semiconductor die. Next, the system receives the first beam of light on an active face of the second semiconductor die and determines a position of the first beam of light on the active face of the second semiconductor die. Finally, the system determines an alignment of the second semiconductor die relative to the first semiconductor die based on the determined position of the first beam of light.

Abstract: A system is presented for latching and amplifying a capacitively coupled inter-chip communication signal that operates by receiving an input signal on a capacitive receiver pad and feeding the input signal through an inverter to produce an output signal. The output signal is fed back through a weakened inverter to produce a feedback signal that is fed into an input of the inverter to form a latch for the input signal. The weakened inverter is biased to produce a feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL. VH is set slightly higher than the switching threshold of the inverter, and VL is set slightly lower than the switching threshold. This feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal.

Abstract: A bi-directional communication system and transceiver configuration are described, which employ a bi-directional reference to account for both common-mode and differential noise introduced at either end of a bi-directional communication channel. Some implementations exploit the techniques described in a bi-directional chip-to-chip communication scheme. In some implementations, the advantages of bi-directional reference techniques described herein are obtained while pre-distortion of transmitted signals is employed to compensate for intersymbol interference (ISI) in a communications channel.

Abstract: A clock interpolation circuit for setting and controlling a phase of an output clock that is derived from an interpolation of multiple input clocks. Interpolation is performed by capacitively weighting the multiple clocks. A select and control circuit provides the ability to select different capacitance values to control the weighting. An optional buffer stage is also provided to sharpen the edge transitions of the interpolated clock.

Abstract: The clock signal is the dominant source of electromagnetic interference (EMI) for many digital electronic devices. EMI generated by these electronic devices must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. The present invention seeks to reduce EMI emissions by phase-modulating the clock signal using tunable delay lines. Phase modulation causes a spreading of the energy spectrum of the clock signal thereby reducing EMI emissions. In addition, the present invention is capable of generating a wide energy spectrum in a short time interval. Furthermore, the present invention can be similarly applied to other signals which exhibit a periodic or timing nature due to a correlation with the clock signal.

Abstract: One embodiment of the present invention provides a system for capacitively probing electrical signals within an integrated circuit. This system operates by placing a probe conductor in close proximity to, but not touching, a target conductor within the integrated circuit. In this position, the probe conductor and the target conductor form a capacitor that stores a charge between the probe conductor and the target conductor. Next, the system detects a change in a probe voltage on the probe conductor caused by a change in a target voltage on the target conductor, and then determines a logic value for the target conductor based on the change in the probe voltage. In one embodiment of the present invention, determining the logic value for the target conductor involves, determining a first value if the probe voltage decreases, and determining a second value if the probe voltage increases.

Abstract: A power converter within an integrated circuit (“IC”) for providing DC power to one or more function circuit, where the power converter has a transformer circuit for receiving an AC power signal and for supplying a transformed AC power signal. A converter circuit receives the transformed AC power signal and then converts the signal into a DC power signal supplied to one or more function circuit. The transformed AC power signal might either be stepped up or stepped down. The transformer circuit might comprise two coils, where a first coil is magnetically coupled to a second coil. The first coil is a first spiral and the second coil is a second spiral wherein an insulating material layer is disposed between the first spiral and the second spiral. The transformer circuit might include transformers connected in parallel or in series and may further be connected correspondingly to more than one converter circuit coupled in parallel.

Abstract: The present invention relates to an integrated circuit device and method of adjusting capacitance of a node of an integrated circuit In one embodiment, the device comprises a first digital input, a first parasitic capacitance block, a first output, a second digital input, a second parasitic capacitance block and a second output. The first parasitic capacitance block includes an inverter, a variable capacitance element, and a wire capacitance element. The first parasitic capacitance block has a capacitance that is a function of the first digital input. The first output is responsive to the first parasitic capacitance block, and the second output is responsive to the second parasitic capacitance block.