Patents by Inventor Robert J. Brainard
Robert J. Brainard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8340523Abstract: A tunable PLC optical filter having sequentially connected thermally tunable Mach-Zehnder (MZ) interferometers is described. The MZ interferometers, having free spectral ranges matching ITU frequency grid spacing, are tuned so as to have a common passband centered on the frequency of the signal being selected, while having at least one of the stopbands centered on any other ITU frequency. Any other optical channel that may be present at any other ITU frequency is suppressed as a result. The PLC chip, including a zero-dispersion lattice-filter interleaver stage, a switchable fine-resolution stage and, or a retroreflector for double passing the filter, is packaged into a hot-pluggable XFP transceiver package. A compensation heater is used to keep constant the amount of heat applied to the PLC chip inside the XFP package, so as to lessen temperature variations upon tuning of the PLC optical filter.Type: GrantFiled: February 20, 2009Date of Patent: December 25, 2012Assignee: JDS Uniphase CorporationInventors: Jinxi Shen, Jyoti K. Bhardwaj, Barthelemy Fondeur, Douglas E. Crafts, Robert J. Brainard, Boping Xie, David J. Chapman
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Publication number: 20090263142Abstract: A tunable PLC optical filter having sequentially connected thermally tunable Mach-Zehnder (MZ) interferometers is described. The MZ interferometers, having free spectral ranges matching ITU frequency grid spacing, are tuned so as to have a common passband centered on the frequency of the signal being selected, while having at least one of the stopbands centered on any other ITU frequency. Any other optical channel that may be present at any other ITU frequency is suppressed as a result. The PLC chip, including a zero-dispersion lattice-filter interleaver stage, a switchable fine-resolution stage and, or a retroreflector for double passing the filter, is packaged into a hot-pluggable XFP transceiver package. A compensation heater is used to keep constant the amount of heat applied to the PLC chip inside the XFP package, so as to lessen temperature variations upon tuning of the PLC optical filter.Type: ApplicationFiled: February 20, 2009Publication date: October 22, 2009Inventors: Jinxi Shen, Jyoti K. Bhardwaj, Barthelemy Fondeur, Douglas E. Crafts, Robert J. Brainard, Boping Xie, David J. Chapman
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Publication number: 20080292239Abstract: The invention relates to waveguiding structures in planar lightwave circuit devices that include a transition region between a slab waveguide and channel waveguides to reduce optical coupling loss. In particular star couplers and arrayed waveguide gratings incorporating the transition region of the present invention demonstrate reduced insertion loss. By creating a transition region composed of transverse rows intersecting the output waveguide array, where the rows have equal dimensions and the effective refractive index is controlled by increasing the spacing width gradually from row to row, an adiabatic transition is created from slab waveguide to channel waveguide array. This structure provides low insertion loss within practical manufacturing tolerances. In addition, the present invention has found that by incorporating the transition region of the present invention into an AWG, the reduced insertion loss can be controlled as uniform insertion loss across the channels.Type: ApplicationFiled: May 23, 2008Publication date: November 27, 2008Applicant: JDS Uniphase CorporationInventors: Barthelemy Fondeur, Edmond J. Murphy, Robert J. Brainard
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Patent number: 7261982Abstract: The present application relates to a method of fabricating planar circuits using a photo lithographic mask set, to the photo lithographic mask set, and to a planar circuit fabricated with the photo lithographic mask set. The instant invention involves separating a photo lithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photo lithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits.Type: GrantFiled: December 15, 2003Date of Patent: August 28, 2007Assignee: JDS Uniphase CorporationInventors: Barthelemy Fondeur, Anca L. Sala, Robert J. Brainard, David K. Nakamoto, Tom Truong, Sanjay M. Thekdi, Anantharaman Vaidyanathan
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Patent number: 7162108Abstract: The invention relates to a variable optical attenuator constructed as a Mach Zehnder planar lightwave circuit, particularly including a channel waveguide support structure for heat isolation and stress relief to reduce polarization dependent loss (PDL) and power consumption in the device. Power reduction trenches comprise longitudinal segments having small stress relief pillars of cladding material left in between them in the etching process. The waveguides of the MZI are supported by a main pillar structure and integral stress relief pillars which remain after removal of the trenches. The waveguide is surrounded by air on three sides for improved heat isolation. The performance of the present invention shows substantial improvement in PDL and extinction ratio over the prior art continuous trench design, and also, to a smaller degree, over the case where power reduction trenches are not used at all.Type: GrantFiled: December 17, 2004Date of Patent: January 9, 2007Assignee: JDS Uniphase CorporationInventors: Anca L. Sala, Duncan W. Harwood, Barthelemy Fondeur, Anantharaman Vaidyanathan, Robert J. Brainard, Sanjay M. Thekdi, Thomas T. Nguyen, Ian Hutagalung
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Publication number: 20040186739Abstract: In accordance with various embodiments of the present invention, an alarm system comprising a controller unit, capable of interfacing with standard alarm sensors and existing alarm panels; a configuration mechanism (such as a web site) through which a user can configure notification parameters and/or contact methods for the different types of events, and an automated dispatching mechanism which serves to make contact with the user, or others designated by the user, as defined by the configuration mechanism, along with data corresponding to the event (e.g., camera image when sensor trips).Type: ApplicationFiled: October 31, 2003Publication date: September 23, 2004Inventors: David Bolles, Robert J. Brainard
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Patent number: 4903199Abstract: Disclosed is a method which speeds up interpretive test program code execution and allows rapid changes to the test code. The tester utilized with the present invention uses the interpretive language TPL (Test Program Language) for device test programs. The present invention uses the first execution of a statement in an interpreted environment to build a table of address value pairs corresponding to the values computed by the statement. It then changes the pseudo code of the statement to use a short assembly language routine to write the values in the table fo their appropriate addresses, using the memory mapped features of the test head hardware. This is done by translating each TPL line into pseudo code as it is loaded. The first time a line of code is executed, it builds a table which contains all the values computed and the addresses to which they are written. The next time the statement is executed, the verb pointer points to the turbo software which is executed rather than the TPL statement.Type: GrantFiled: April 19, 1988Date of Patent: February 20, 1990Assignee: Texas Instruments IncorporatedInventors: W. Russ Keenan, Stephen F. Comen, Robert J. Brainard
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Patent number: D442938Type: GrantFiled: January 21, 2000Date of Patent: May 29, 2001Assignee: Shure IncorporatedInventors: Jack Brian Hough, Robert J. Brainard
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Patent number: D404736Type: GrantFiled: January 26, 1998Date of Patent: January 26, 1999Assignee: Shure Brothers IncorporatedInventors: Jason Joel Alvarez, Robert J. Brainard
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Patent number: D851529Type: GrantFiled: October 19, 2016Date of Patent: June 18, 2019Assignee: Honeywell International Inc.Inventors: Robert J. Brainard, Rebecca J. Peterson
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Patent number: D896115Type: GrantFiled: June 18, 2019Date of Patent: September 15, 2020Assignee: Honeywell International Inc.Inventors: Robert J. Brainard, Rebecca J. Peterson
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Patent number: D896116Type: GrantFiled: June 18, 2019Date of Patent: September 15, 2020Assignee: Honeywell International Inc.Inventors: Robert J. Brainard, Rebecca J. Peterson
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Patent number: D896673Type: GrantFiled: June 18, 2019Date of Patent: September 22, 2020Assignee: Honeywell International Inc.Inventors: Robert J. Brainard, Rebecca J. Peterson