Abstract: An apparatus and method for supporting PCI Express is disclosed. A physical layer has a PCI Express interface for receiving data from a PCI Express compatible communication medium. The data is in the form of a packet. A data link layer is disclosed for verifying a CRC value and a sequence number received within the packet. A transaction layer is disclosed for receiving the packet from the data link layer and for processing thereof. The transaction layer processes at least some of the packet data in parallel to the data link layer.

Abstract: A system and method for packet-based communications is performed by implementing arbitrated packet-based communications. According to an example embodiment, packet-based data is arbitrated and output with verification data. For each arbitrated packet stream, verification data is generated in response to detecting an end of frame (EOF) symbol in the arbitrated packet stream, and the verification data is added to the packet stream. A merged packet stream is provided at an output, the merged packet stream including the plurality of arbitrated packet streams with verification data added thereto.

Abstract: A system and method for packet-based communications is performed by implementing arbitrated packet-based communications. According to an example embodiment, packet-based data is arbitrated and output with verification data. For each arbitrated packet stream, verification data is generated in response to detecting an end of frame (EOF) symbol in the arbitrated packet stream, and the verification data is added to the packet stream. A merged packet stream is provided at an output, the merged packet stream including the plurality of arbitrated packet streams with verification data added thereto.

Abstract: In one example embodiment, data is transferred at high speeds over a parallel data bus without loss of data integrity by transferring the data encoded with the quantity of ones relatively the same as the quantity of zeroes. Consistent with one embodiment of the present invention, a bus-interface circuit encodes a set of X data bits into a set of Y data bits, where Y is greater than X. The encoding is implemented to approximately balance the number of ones and the number of zeroes in each set to be transmitted. A specific example application involves encoding the set of X data bits so that there is a balanced number of ones and zeroes in the set of Y data bits. In certain applications, the present invention is implemented to reduce current flow between transmitting and receiving modules and thereby reduce EMI, reduce the number of power pins required for the bus interface, and/or reduce the I/O delay and the skew from voltage sag in the signals passed over the parallel data bus.

Abstract: A method for determining the illumination of an illuminator at a selected point P in an image volume to be projected on an image screen surface by a computerized image generator, operates by: decomposing the illuminator into at least one of spherical, beam and cylindrical sources; determining a direction of incidence of the light from each source at point P in the image volume; determining the extent of the source and the attenuation of illumination with distance from that source; then determining a set of color light intensities at point P in the image volume due to the light from the particular source; and translating the incidence direction and color intensities from point P to a displayable incidence direction and a displayable set of color illumination intensities at a corresponding projection location on the image screen surface.