Abstract: An apparatus, system, and method are generally related to an antenna device that includes a pass-through interface such as for a USB device. The antenna device is enclosed in a housing. The pass-through interface includes two ports. The housing is coupled to the pass-through interface body such that one of the ports is blocked by a blocking member when the housing is in a first position. The blocking member prevents impact damage to the blocked port, while also preventing dirt and dust from collecting. The blocking member is cleared from the opening of the blocked port when the housing is biased into a second position by inserting a connector. The blocking member automatically returns to the first position when the connector is removed from the port. Antenna performance is improved by automatically aligning the antenna away from the connector, which may otherwise degrade performance.

Abstract: An apparatus, system, and method are generally related to an antenna device that includes a pass-through interface such as for a USB device. The antenna device is enclosed in a housing. The pass-through interface includes two ports. The housing is coupled to the pass-through interface body such that one of the ports is blocked by a blocking member when the housing is in a first position. The blocking member prevents impact damage to the blocked port, while also preventing dirt and dust from collecting. The blocking member is cleared from the opening of the blocked port when the housing is biased into a second position by inserting a connector. The blocking member automatically returns to the first position when the connector is removed from the port. Antenna performance is improved by automatically aligning the antenna away from the connector, which may otherwise degrade performance.

Abstract: An apparatus, system, and method are generally related to an antenna device that includes a pass-through interface such as for a USB device. The antenna device is enclosed in a housing. The pass-through interface includes two ports. The housing is coupled to the pass-through interface body such that one of the ports is blocked by a blocking member when the housing is in a first position. The blocking member prevents impact damage to the blocked port, while also preventing dirt and dust from collecting. The blocking member is cleared from the opening of the blocked port when the housing is biased into a second position by inserting a connector. The blocking member automatically returns to the first position when the connector is removed from the port. Antenna performance is improved by automatically aligning the antenna away from the connector, which may otherwise degrade performance.

Abstract: The present invention provides a new architecture for MMIC circuitry that allows reception of electronically selectable single polarity for simultaneous dual polarity/dual beam signals by phased-array modules. Additionally, an improved phase shifter design that is smaller and requiring fewer electronic components than prior art phase shifters is disclosed. In particular, the phase shifter requires only a single control line for each stage of the phase shifter.

Abstract: The present invention provides a new architecture for MMIC circuitry that allows reception of electronically selectable single polarity or simultaneous dual polarity/dual beam signals by placed-array modules. Additionally, an improved phase shifter design that is smaller said requiring fewer electronic components than prior art phase shifters is disclosed. In particular, the phase shifter requires only a single control line for each stage of the phase shifter.

Abstract: The present invention provides a new architecture for MMIC circuitry that allows reception of electronically selectable single polarity or simultaneous dual polarity/dual beam signals by phased-array modules. Additionally, an improved phase shifter design that is smaller and requiring fewer electronic components than prior art phase shifters is disclosed. In particular, the phase shifter requires only a single control line for each stage of the phase shifter.

Abstract: A power splitter (10), including a feedback amplifier (16) and matching network (18), is disclosed for splitting the output of a signal source (12) to be applied to a processing system (14). The feedback amplifier includes a gain stage (20) and active load (22). The gain stage includes a field-effect transistor (FET) (Q1) and feedback components (LF and RF) that provide the amplification required to give the power splitter unity gain. An inductive element (LD) gives the amplifier the desired bandwidth and a dual-gate FET (Q2) is employed as the active load to reduce loading of the gain stage. The matching network includes a plurality of stages (e.g., 24), each of which includes a source follower FET (e.g., Q3 ) and a single-gate active load FET (e.g., Q4). The resultant power splitter provides the desired equal power, matched phase outputs with suitable isolation and minimal insertion losses.