Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a Boolean combination of the three inputs that is selected by a function signal. The arithmetic logic unit is capable of forming all possible Boolean combinations of the three inputs. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal optionally comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal optionally comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239).

Abstract: A system (26) for stabilizing a video recording of a scene (20, 22, & 24) made with a video camera (34) is provided. The video recording may include video data (36) and audio (38) data. The system (26) may include source frame storage (64) for storing source video data (36) as a plurality of sequential frames. The system (26) may also include a processor (50) for detecting camera movement occurring during recording and for modifying the video data (36) to compensate for the camera movement. Additionally the system (26) may include destination frame storage (70) for storing the modified video data as plurality of sequential frames.

Abstract: A three input arithmetic logic unit (230) generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shift (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal.

Abstract: A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal.

Abstract: A television system 106 and display method for receiving and displaying television broadcasts having various formats. The television system resizes (106) the various received image formats for display on a common display device. Images are resized horizontally by altering the rate at which data is sampled by the television (106). Images are resized vertically by using vertical scaling algorithms which alter the number of lines in an image. Format detection may be done automatically by decoding information contained in the vertical interval of the television broadcast signal, or by counting the number of lines in each frame. The input format may be indicated by a viewer.

Abstract: There is disclosed a multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The image processor is structured with several individual processors all having communication links to several memories. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

Abstract: A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. A base address instruction executing on any one of the processors generates the base address corresponding to that processor.

Abstract: A method of pulse width modulation using a spatial light modulator (40) with a finite transition time. The method uses m bits per sample to digitize the incoming data, but apportions the LSB times for pulse width modulation based upon m-1 bits. The current video frame displays all of the bits for each sample, except for the LSBs for each sample. The next video frame displays all of the bits for each sample, adding one more LSB for dividing up the frame time. The first frame could use either the additional LSB time and display no data, or it could use only that number of LSB times it needs. In the latter, the system will have to adjust to different partitions of the frame time for alternating frames. The system includes a spatial light modulator (40), a memory (42), a formatter (48), a sequence controller (44) and a toggle circuit (46), to perform this method.

Abstract: A line generator (31) for receiving fields of pixel data sampled from a video input signal and for generating additional lines of pixel data so that the display frames will have more lines than the fields. The line generator (31) has a motion detector (31a) that determines, on a pixel by pixel basis, whether some part of the current field is in motion. A motion signal from the motion detector (31a) is used to select between outputs of two or more pixel generators (31b, 31c). One of the pixel generators (31b) provides pixel values that are better suited for display when the image is not in motion. The other pixel generator (31c) provides pixel values that are better suited for display when the image is in motion.

Abstract: Conditional hardware branching employs zero overhead loop logic and writing to a loop count register within a program loop. The zero overhead loop logic includes a program counter (701), loop end registers (711, 712, 713), loop start registers (721, 722, 723), loop counter registers (731, 732, 733), comparators (715, 716, 717) and loop priority logic (725). Normally the program counter (701) is incremented each cycle. The comparators (715, 716, 717) compare the address stored in the program counter (701) with respective loop end registers (711, 712, 713). If the address in the program counter (701) equals a loop end address, loop priority logic (725) decrements the loop count register and loads the program counter with the loop start address in loop start register. Hardware looping involves loading a loop count register during program loop operation.

Abstract: A method and structure for a display system having multiple spatial light modulators (SLMs) (16), each of which contributes an image of one color that is perceived by the viewer as a combined image. The SLMs (16) have more rows and columns of pixel elements (42) than rows or columns of pixel data to be displayed. A window of "active" pixel elements (42) can be shifted up and down or right and left by selecting which pixel elements (42) are to receive data. The addressing circuit (31, 31a, 35, 35a) of each SLM 16 can be controlled so as to accomplish this shifting.

Abstract: The invention involves communication within a multiprocessor system. The multiprocessor system includes a command word bus and a plurality of data processors. Each data processor is connected to the command word bus and includes a command circuit, a decoder and a reset control circuit. The command circuit may generate a command word on the command word bus including at least one reset command word for resetting a data processor. The decoder decodes command words received via the command word bus and includes at least a reset command decoder for decoding a reset command word. The reset control circuit resets the data processor into a state corresponding to initial application of electrical power upon receiving a reset command word. Each command word circuit generates command words indicating a particular data processor to which it is directed. Only a predetermined subset of the data processors may send the reset command word directed to other data processors.

Abstract: A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. Each processor has a register with a plurality of read only bits which uniquely identify that processor within the multi-processing system. The processor may employ this unique processor identifier to compute the base address corresponding to that processor.

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shifter could be a left barrel rotator with wrap around or a controllable left/right shifter. The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being a left shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result.

Abstract: A data processor includes both integer and floating point operation units and operates as a reduced instruction set computer (RISC). A modification of the normal load/store RISC operations includes within in its instruction set some instructions that permit floating point operations to be paired with load or store operations. These operations include: vector floating point add; vector multiply accumulate; vector floating point multiply; vector multiply subtract; vector reverse subtract; vector round floating point input; vector round integer input; and vector floating point subtract.

Abstract: A motion adaptive method for vertically scaling an image. The image data is analyzed to obtain a motion magnitude value for each pixel (31). The pixel data is then processed with two scaling processes (35, 36), performed in parallel. One scaling process is better suited for low motion images and the other is better suited for high motion images. The motion magnitude value is used to select between or combine (38) the pixel data outputs of the two scaling processes (35, 36).

Abstract: A SLM-based projection display system (10) samples and processes video data for delivery to a spatial light modulator (SLM) (13c), and uses a color wheel (14a) to color the SLM-generated images. A frame memory (13b) provides data to the SLM (13c) and is managed so that, if the phase of the incoming video signal changes, a desired phase relationship between the color wheel position and the data available to the SLM (13c) can be maintained. Also, a motor control unit (15a) uses a horizontal sync signal to generate a drive signal for the color wheel motor (16a), which limits the transient time during phase-changing events, and which provides a means for adjusting the phase of the drive signal.

Abstract: A method of reducing artifacts in SLM-based display systems (10, 20), whose images are based on data displayed by bit-weight for pulse-width modulated intensity levels. The method can be used with a multiple spatial light modulators SLM system (20), which concurrently displays images of different colors, or with a single SLM system (10), which generates differently colored images sequentially during each frame period. For a multiple SLM system (20), the method is used with SLMs (14) that are memory-multiplexed, having "reset groups" that are loaded and displayed at different times. Corresponding rows of the SLM(s)s are associated with different reset groups.

Abstract: This invention is a manner of control of the addresses of memory accesses. The data processing device of this invention includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, a number of guide table entries and a table pointer. The guide table includes guide table entries, each guide table entry having an address value and dimension values defining a block of addresses. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values.