Patents by Inventor Robert J. Halford

Robert J. Halford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200218595
    Abstract: The present disclosure relates to novel and advantageous systems and methods of processing and managing data in critical or large-scale systems, such as airliner, automobile, space station, power plant, and healthcare systems. Particularly, the present disclosure relates to a rules-driven data and control method mapped onto complementary physical architecture for a more reliable operational system. By maintaining an algebraic encoding of control and application data at fine granularities, whether static or in transit, it is possible to detect, isolate, and correct many errors that would otherwise go undetected. This more dynamic and precise method addresses cases where deteriorating conditions or cataclysmic events affect much of the system simultaneously, including the control system itself.
    Type: Application
    Filed: February 11, 2020
    Publication date: July 9, 2020
    Applicant: Chippewa Data Control LLC
    Inventor: Robert J. Halford
  • Patent number: 10599511
    Abstract: The present disclosure relates to novel and advantageous systems and methods of processing and managing data in critical or large-scale systems, such as airliner, automobile, space station, power plant, and healthcare systems. Particularly, the present disclosure relates to a rules-driven data and control method mapped onto complementary physical architecture for a more reliable operational system. By maintaining an algebraic encoding of control and application data at fine granularities, whether static or in transit, it is possible to detect, isolate, and correct many errors that would otherwise go undetected. This more dynamic and precise method addresses cases where deteriorating conditions or cataclysmic events affect much of the system simultaneously, including the control system itself.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: March 24, 2020
    Assignee: Chippewa Data Control LLC
    Inventor: Robert J. Halford
  • Publication number: 20180018216
    Abstract: The present disclosure relates to novel and advantageous systems and methods of processing and managing data in critical or large-scale systems, such as airliner, automobile, space station, power plant, and healthcare systems. Particularly, the present disclosure relates to a rules-driven data and control method mapped onto complementary physical architecture for a more reliable operational system. By maintaining an algebraic encoding of control and application data at fine granularities, whether static or in transit, it is possible to detect, isolate, and correct many errors that would otherwise go undetected. This more dynamic and precise method addresses cases where deteriorating conditions or cataclysmic events affect much of the system simultaneously, including the control system itself.
    Type: Application
    Filed: July 14, 2017
    Publication date: January 18, 2018
    Inventor: Robert J. Halford
  • Patent number: 5347637
    Abstract: A modular input-output subsystem for a supercomputer is disclosed. Peripheral devices are coupled to the system through channel adaptor interfaces, while communication with the CPU is through high speed data channels. A memory buffer is provided to buffer data transfers between the peripherals and the Central Processing Units (CPUs) and the Solid State Storage Devices (SSDs).
    Type: Grant
    Filed: August 8, 1989
    Date of Patent: September 13, 1994
    Assignee: Cray Research, Inc.
    Inventor: Robert J. Halford
  • Patent number: 5283791
    Abstract: The present invention discloses an error recovery method for parallel architecture data storage devices. The present invention provides means for simultaneously arranging data on a plurality of recording surfaces so that intermittent and/or solid failures do not prevent access to the data stored thereon. A first error correcting code comprising a parity bit is generated for each dataword. The dataword and the parity bit are stored simultaneously and bit-wise to a plurality of recording surfaces. A second error correcting code is generated for a plurality of bits transmitted to a specific recording surface. The second error correcting code is written onto the same recording surface as the bits from which it was generated. The second error correcting code is used to detect and correct intermittent errors in the data read from a particular recording surface.
    Type: Grant
    Filed: March 18, 1993
    Date of Patent: February 1, 1994
    Assignee: Cray Research Systems, Inc.
    Inventor: Robert J. Halford
  • Patent number: 5128810
    Abstract: A multiple disk drive array storage device is described which emulates the operation of a single disk drive so that the handshaking and protocol between the array storage device and the host computer appears to the host computer to be that of a single disk drive. The array storage device includes a plurality of individual disk drives, each of which having its spindle synchronized to the other disk drives using a master clock synchronization. Digital data words are received by the array storage device controller which divides the words into subparts and writes each subpart to a different disk drive within the storage device. The buffering and formatting of the digital data for reading and writing from the individual disk drives is accomplished by the controller transparent to the host computer.
    Type: Grant
    Filed: July 3, 1991
    Date of Patent: July 7, 1992
    Assignee: Cray Research, Inc.
    Inventor: Robert J. Halford
  • Patent number: 4807121
    Abstract: A peripheral interface system is disclosed. An input-output processor is provided to receive input-output commands from a central processing unit. Up to four multiplexing units may be connected to the input-output processor, with each multiplexing unit providing an interface for up to four controller units, which may be used to control a peripheral device. The multiplexing unit includes a pair of data buffers, each with its own addressing circuit, and each functionally divided into four storage areas, each storage area providing four registers to store four parcels of data. Data is transferred between the input-output processor and the controller units by filing the storage area in a buffer from the local memory of the input-output processor in a serial fashion over a DMA channel provided between the multiplexer and the local memory.
    Type: Grant
    Filed: June 10, 1988
    Date of Patent: February 21, 1989
    Assignee: Cray Research, Inc.
    Inventor: Robert J. Halford
  • Patent number: 4771378
    Abstract: An electrical interface system provides a set of signals to be used in transferring information between first and second terminals. To transfer information from the first terminal to the second terminal, a WRITE CLOCK, FUNCTION/DATA READY, four CODE, one CODE PARITY, 16 DATA and DATA PARITY signals are provided. To transfer information from a second terminal to the first terminal, a READ CLOCK, STATUS/DATA READY, ERROR, DONE, INDEX/SECTOR MARK, STATUS PARITY, 16 DATA and one DATA PARITY signals are provided. The four CODE signals may be formed to signal any one of a plurality of requested functions to the second terminal, while the second terminal may indicate its general status to the first terminal with the ERROR, DONE, READY and MARK signals, each terminal capable of further defining functions or status by formation of words with the data signals.
    Type: Grant
    Filed: June 19, 1984
    Date of Patent: September 13, 1988
    Assignee: Cray Research, Inc.
    Inventor: Robert J. Halford