Abstract: A Recovery Control Register is embodied as two multi-bit registers; a staged register and an immediate register. The immediate register contains the information which is read by the CP microcode and used during recovery. The staged register is a platform where a footprint can be assembled by the CP microcode before the retry checkpoint is changed. The CP microcode can operate on either register through the use of "SET", "AND" and "OR" functions. The choice of these operators as well as the decision to separate the registers into bit ranges provides the microcode with maximum flexibility when setting up new checkpoint values. When a recovery algorithm requires that the recovery footprint change immediately, microcode operates on the immediate register.

Abstract: An improved error recovery system in which all operations which the Central Processor performs are categorized into one of a plurality of recovery types. The determination of category is made based on which architected and machine dependent facilities they manipulate and the manner in which the facilities are manipulated. This classification of instructions into types allows for the amount of checkpoint data to be minimized while allowing recovery to be generalized into broad algorithms instead of handling each operation independently. Furthermore, by applying this classification technique to various phases of execution (recovery windows) of instructions which modify system facilities before they complete, these instructions can also be retried with a minimum of hardware and algorithms.

Abstract: A method of handling errors in the C bit of a storage key by modifying the INSERT STORAGE KEY (ISK) and the RESET REFERENCE BIT (RRB) instructions. If an error is found in the C bit during the execution of these instructions, microcode is instructed to refresh the C bit. The C bit is interrogated a second time to determine if the refreshed C bit is still in error. If the refreshed C bit is not in error a second time, then the first error was caused by a soft or transient error, and the instruction is continued. If the refreshed C bit is in error a second time then the first and second errors were caused by a permanent error such as a stuck bit, and a system recovery machine check error is generated. The handling of C bit errors is thus done in a dynamic fashion as the instructions are executed.