Patents by Inventor Robert J. Lessard

Robert J. Lessard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6204094
    Abstract: A method for assembling electronic devices by moving particles (12) on an adhesive sheet (35) having a plurality of adhesive areas (30), comprising the steps of loading the particles (12) onto the adhesive sheet (35) and transferring kinetic energy from a mechanical device (39) to the particles (12) for moving the particles (12) is disclosed. The adhesive sheet (35) may be composed of an adhesive coating (22) laminated to a film (24). The particles (12) may be composed of a variety of materials, including minerals and compounds such as solder or polymers.
    Type: Grant
    Filed: February 2, 1999
    Date of Patent: March 20, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory B. Hotchkiss, Robert J. Lessard
  • Patent number: 5024746
    Abstract: This disclosure describes a plating fixture to hold a silicon wafer containing integrated circuits in a metal plating bath. The wafer is coated with photoresist to a thickness equal to the desired bump height and the desired bump locations patterened by standard photolithographic techniques. The wafer is then loaded in the fixture and the fixture placed in the plating bath so that the patterned side of the wafer is facing up and the plating anode is located directly above the wafer. Systems presently on the market have the wafer positioned with the patterned side facing down and the anode located below it, or the wafer faces sideways and the anodes are access from it. These present systems allow air to be entrapped in the pattern of the photoresist, lowering yield by under plating or uneven plating of the bumps on the wafer. This disclosure prevents such yield loss and also allows cleanups on the wafer after it is loaded in the fixture.
    Type: Grant
    Filed: May 14, 1990
    Date of Patent: June 18, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Roger J. Stierman, Robert J. Lessard
  • Patent number: 4931149
    Abstract: This disclosure describes a plating fixture to hold a silicon wafer containing integrated circuits in a metal plating bath. The wafer is coated with photoresist to a thickness equal to the desired bump height and the desired bump locations patterned by standard photolithographic techniques. The wafer is then loaded in the fixture and the fixture placed in the plating bath so that the patterned side of the wafer is facing up and the plating anode is located directly above the wafer. Systems presently on the market have the wafer positioned with the patterned side facing down and the anode located below it, or the wafer faces sideways and the anodes are access from it. These present systems allow air to be entrapped in the pattern of the photoresist, lowering yield by under plating or uneven plating of the bumps on the wafer. This disclosure prevents such yield loss and also allows cleanups on the wafer after it is loaded in the fixture.
    Type: Grant
    Filed: January 10, 1989
    Date of Patent: June 5, 1990
    Assignee: Texas Instruments Incorporated
    Inventors: Roger J. Stierman, Robert J. Lessard