Patents by Inventor Robert J. Mattox

Robert J. Mattox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5217920
    Abstract: A method of fabricating a semiconductor structure includes providing a substrate having at least one layer formed thereon. At least two trenches are formed through the layer and into the substrate wherein at least one trench is for isolation and at least one trench is for making contact to the substrate. After a trench liner is formed on the sidewalls of the trenches, the trenches are filled with doped semiconductor material. The doped semiconductor material in the trench for isolation is then anodized. After the anodization, the anodized trench fill material is oxidized.
    Type: Grant
    Filed: June 18, 1992
    Date of Patent: June 8, 1993
    Assignee: Motorola, Inc.
    Inventors: Robert J. Mattox, Paul R. Proctor, Syd R. Wilson
  • Patent number: 4943539
    Abstract: A method for forming a via contact for devices having multilayer metallization is provided wherein a sacrificial layer is formed over a bottom interconnect layer, and an interlayer dielectric is formed on the sacrificial layer. A via is etched in the interlayer dielectric, exposing the sacrificial layer. The sacrificial layer is isotropically etched to expose an area of the interconnect metal that is larger than the area of the via and a via metallization is selectively formed on the interconnect metal by chemical vapor deposition so that the via, including a void created by the isotropic etch of the sacrificial layer, is filled with the via metallization, thereby providing a contact area to the bottom interconnect metal which is larger than the via metallization itself.
    Type: Grant
    Filed: May 9, 1989
    Date of Patent: July 24, 1990
    Assignee: Motorola, Inc.
    Inventors: Syd R. Wilson, James A. Sellers, Robert J. Mattox
  • Patent number: 4801350
    Abstract: A method for the construction of submicron features using optical lithography technology. A material is deposited on a surface to be etched, this material is partially etched through using optical lithography technology. Sidewalls are deposited to reduce the size of this etched area to the submicron size desired. The etch of the layer is then completed resulting in a submicron mask for the substrate below.
    Type: Grant
    Filed: December 29, 1986
    Date of Patent: January 31, 1989
    Assignee: Motorola, Inc.
    Inventors: Robert J. Mattox, Frederick J. Robinson
  • Patent number: 4791073
    Abstract: A method is described for forming dielectric filled isolation trenches in semiconductor substrates in which a differentially etchable etch-stop layer is provided above the surface of the substrate during the trench filling process so that the height of the trench filling relative to the surface of the substrate may be adjusted for optimum overall results during subsequent fabrication steps and so that the substrate surface may be protected from contact with the etching reagents used during planarization of the trench filling material. This avoids damage to the substrate surface and permits improved surface planarity.
    Type: Grant
    Filed: November 17, 1987
    Date of Patent: December 13, 1988
    Assignee: Motorola Inc.
    Inventors: Andrew G. Nagy, Robert J. Mattox