Abstract: Multiple processing systems each inclue an administrator processor and a plurality of intelligent resources (like a printer, encoder, for example) which are coupled to the associated administrator processor via a local area network (LAN). Each administrator processor is coupled to two pluralities or sets of intelligent resources with one set being connected through a primary connection node of the associated administrative processor and with the other set being connected to an associated secondary connection node. Each administrator processor is also directly coupled to exactly two other administrator processors through its associated primary and secondary connection nodes to form a closed ring network. An intelligent resource normally assigned to one administrator processor may be assigned (if available) to an adjacent administrator processor to reallocate the workload in the ring network and adjust to certain failures in the system.

Abstract: A system for improving the processing of financial transactions using direct customer entry of the transaction data and automatic verification of this data during proof operations. Each customer prepares his own transaction slip via a remote terminal, which slip is delivered to a teller for verification. During proof and encoding operations, the amount field of each document is read and composed with the data entered by the customer for correspondence; any errors may be corrected at this stage for reconciliation, saving time and labor costs.

Abstract: A method and apparatus for removing erroneous data elements from digital images by systemically moving a window memory over the entire area of an image. Each data element in the image is examined with respect to neighboring elements by comparing the contents of the window with a set of masks to determine if a certain data element should be altered.

Abstract: A microprocessor is programmed to generate reference envelopes of a specified time duration and synchronized with clock pulses, and circuit means is associated with such microprocessor for indicating desired speed of a prime mover through comparison of prime mover actual speed with said reference envelope, and means is provided for adjusting prime mover speed to correspond with such reference envelope.