Abstract: A congestion management technique achieves an end-to-end data flow rate that is supported by a lossless communications network. The end-to-end rate extends from a source end node to destination end node of the network and is preferably at or slightly below a bottleneck rate of the network. The destination end node determines, on its own and without any help from network elements, a supportable rate of activity in the network and provides feedback to the source end node. By achieving such a rate, data transmitted by the source end node can flow through the network without loss of packets and without the use of substantial buffering.

Abstract: A switching method and apparatus operates as a work conserving network device. An arbiter using an arbitration algorithm controls a switch fabric interconnecting input ports and output ports. To switch cells, a virtual output queue of an input port is selected that corresponds to an output port with a lowest occupancy rating and a request is sent to this output port. In a greedy version of the algorithm, input ports may send requests to the lowest occupied output port for which they have a cell. In a non-greedy version, requests may only be sent if that input port has a cell for the lowest occupied output port in the entire network device. An output port that receives one or more requests from input ports uses an input port selection algorithm to select an input port from which to receive a packet. After as many input and output ports are matched as is possible in a phase, the packets for those matched ports are transferred across the switch.

Abstract: A switching method and apparatus operates as a work conserving network device. An arbiter using an arbitration algorithm controls a switch fabric interconnecting input ports and output ports. To switch cells, a virtual output queue of an input port is selected that corresponds to an output port with a lowest occupancy rating and a request is sent to this output port. In a greedy version of the algorithm, input ports may send requests to the lowest occupied output port for which they have a cell. In a non-greedy version, requests may only be sent if that input port has a cell for the lowest occupied output port in the entire network device. An output port that receives one or more requests from input ports uses an input port selection algorithm to select an input port from which to receive a packet. After as many input and output ports are matched as is possible in a phase, the packets for those matched ports are transferred across the switch.

Abstract: An arbitration scheme for providing deterministic bandwidth and delay guarantees in an input-buffered crossbar switch with speedup S is presented. Within the framework of a crossbar architecture having a plurality of input channels and output channels, the arbitration scheme determines the sequence of fixed-size packet (or cell) transmissions between the inputs channels and outputs channels satisfying the constraint that only one cell can leave an input channel and enter an output channel per phase in such a way that the arbitration delay is bounded for each cell awaiting transmission at the input channel. If the fixed-sized packets result from fragmentation of variable size packets, the scheduling and arbitration scheme determines deterministic delay guarantees to the initial variable size packets (re-assembled at the output channel) as well.

Abstract: A content addressable memory (CAM) structure, and a method for its use, wherein data items of different selected lengths stored in the CAM may be located by matching sequences of CAM data words with sequences of input data words. Extension bits associated with each CAM data word control a sequence of comparison cycles to permit an input data item to be compared simultaneously with multiple input data items of the same length stored in the CAM structure. The CAM structure can be used without modification to store data items of various selected lengths. A begin bit associated with each CAM data word is used to mark the beginning of each stored data item and, in an exact match mode of operation, a global line is used to mark the beginning of an input data item. Match logic associated with each CAM data word generates a match till now signal in each comparison cycle, and the signal is propagated to the end of the data item if an exact match is detected.

Abstract: A method of scheduling the transmission of cells from a network node involves storing entries in a schedule table at predetermined locations, wherein each location represents a point in time at which a cell is to be transmitted. Each entry in the table contains a pointer to a list of virtual circuits having cells scheduled for transmission at the time corresponding to the location of the entry in the table. When a VC has a cell to be transmitted at a particular time, the VC is queued to the head, rather than the tail, of the list of VCs pointed to by the pointer located at the entry in the table corresponding to the time at which the cell is to be transmitted. The VC is therefore the first VC transmitted from the list of VCs.

Abstract: A method and apparatus for transferring data units between a host memory and a peripheral interface, the data units being subject to a flow control mechanism whereby some of said data units are flow controlled and some of said data units are not. Two transmit buffer memories are coupled to the peripheral interface; one for storing controlled data units to be transferred to the peripheral interface and the other for storing uncontrolled data units to be transferred to the peripheral interface. A single request buffer stores successive requests for data to be transferred from a host memory to either of the two transmit buffer memories. Data transfer circuitry transfers data from the host memory to either of the two transmit buffer memories in response to the requests stored in the request buffer.

Abstract: A flow control system is disclosed, for a transmitting node and a receiving node. The transmitting node and the receiving node are linked together through multiple connections or virtual circuits. A flow control circuit in the transmitting node limits the number of data transmission units transmitted from the transmitting station, and not yet copied out of the receive buffers in the receiving node, to the total number of receive buffers in the receiving node. The flow control circuit in the transmitting node further controls the transmission of data transmission units on the multiple connections fairly, such that all connections are provided a proportional amount of the total available receive buffers in the receiving node. In an example embodiment, a global counter is used to maintain the total number of receive buffers containing data in the receiving node, and a global limit register contains the maximum number of receive buffers containing data in the receiving node allowed for a single connection.

Abstract: A computer system having an arbitration mechanism for controlling the coupling order between a plurality of requesters and a plurality of resources, where each resource has an associated resource type. The arbitration mechanism includes a plurality of request processing units, each associated with one of the plurality of requesters. The request processing units receive resource type request signals from an associated requester. The arbitration mechanism also includes a plurality of grant processing units, each associated with one of the plurality of resources. The grant processing units monitor a status signal from its associated resource. The arbitration mechanism further includes a common broadcast medium which is coupled to all of the request processing units and grant processing units.

Abstract: A packet data communication network employs a local switch, router or bridge device functioning to transfer packets between segments of a larger network. When packets enter this device, an address translation is performed to generate local source and destination addresses which are much shorter than the globally-unique addresses contained in the packet as dictated by the protocol. These local addresses are inserted in a header that is added to the packet, in addition to any header already contained in the packet. This added header travels with the packet through the local switch, router or bridge device, but then is stripped off before the packet is sent out onto another network segment. The added header may also contain other information, such as a local name for the source and destination segment (link), as well as status information that is locally useful, but not part of the packet protocol and not necessary for transmission with the packet throughout the network.

Abstract: An arbitration mechanism for controlling a coupling order between a number of resources and a number of requesters having a number of requests processing units, one associated with each one of the requesters, for receiving a resource type request signal from the associated requester, a number of grant processing units, one associated with each one of the resources, for monitoring a busy status signal from said associated resource, a common broadcast medium coupled to the number of request processing units and the grant processing units, and an arbiter for granting access to said common broadcast medium to one of the request processing units and the grant processing units using the common broadcast medium to control the coupling order between the requesters and the resources in a first come, first served manner.

Abstract: A plug-in logic board for use in an arbitration mechanism is disclosed. The disclosed arbitration mechanism includes two or more request processing units, two or more grant processing units and a common broadcast medium. The request processing units and the grant processing units use the common broadcast medium to control the coupling between requesters and resources on a first come, first served basis. The disclosed logic board includes a request processing unit coupled to the common broadcast medium, a grant processing unit coupled to the common broadcast medium, and an input/output unit coupled to an electronic operating device. The input/output unit passes a resource type request signal from the electronic operating device to the request processing unit, and passes a status signal received from the electronic operating device to the grant processing unit. The input/output unit further outputs a grant signal received from the request processing unit to the electronic operating device.

Abstract: A fast arbiter for handling a large number of types of resources with multiple instances of each type of resource is provided. During a first cycle a request logic circuit broadcasts a request for a preselected type of resource onto a broadcast medium. During a second cycle a grant logic circuit broadcasts a queue position onto the broadcast medium for the preselected type of resource. Also, during the second cycle the request logic circuit stores the queue position. After an asynchronous wait for an instance of the requested type of resource to become free, a third cycle begins wherein the first grant logic circuit broadcasts an indication that a free instance of the preselected type of resource is available. During a fourth cycle the requester is granted access to the free instance of the preselected type of resource.

Abstract: An injection molded aluminum nitride heatsink forms the substrate of an integral heatsink semiconductor package in which a semiconductor chip is attached directly to the integrated heatsink forming an intimate thermal relationship between the heat generating source and the heat dissipating means. In a first embodiment, a planar surface of the heatsink component provides the substrate for the attachment of a semiconductor chip and a multilayer housing formed from a plurality of layers of dielectric glass ceramic lamina and conductive circuit layers. The multilayer housing is formed on top of the heatsink substrate creating a recessed cavity in which the semiconductor die sits and is attached directly to the heatsink. The semiconductor chip is attached to the circuit layers of the housing through any of the known electrical connection methods, such as wirebonding or tab tape. A cover plate is mounted over the cavity.

Abstract: A crossbar switch consists of a control computer, and a switching matrix which includes a number of switching cells in which connections between data input lines and data output lines are made. The switch operates to simultaneously connect to data output lines initially active data input lines and disconnect therefrom inactive data input lines. Each data input line is associated with an activity logic circuit which monitors activity on the line. The activity logic circuits connect to the control computer and inform it when an inactive data input line becomes active and requires a connection. The activity logic circuits further inform the control computer of the status of connected data input lines each time the control computer performs a connection operation. To make a connection, the control computer energizes a column enable line corresponding to the requested data output line and leaves de-energized the column enable lines corresponding to the other data output lines.

Abstract: A digital communications system includes a transmitting section that receives electrical signals in parallel and transmits them serially by means of an optic fiber (10) to a receiving section (11). A sampler/filter (20) samples the incoming electrical signals at a rate several times that of the maximum data rate expected of those signals and employs majority-vote circuits (116) to change the value of any samples that are not part of a plurality of sequential samples of the same value. The achieve as balanced a signal as possible, a complementing unit (36) complements alternate groups of bits, and a coding unit (40) imposes a 4-to-5 code in which the code-word imbalances for complementary data words are opposite in the majority of cases.

Abstract: A data link (1000) multiplexes a large number of concurrently operating channel onto a single pair of fiber-optic cables (10 and 1010). A receiver (1004A) at one end of the links determines whether it is in sychronism with the signals that it receives over one of the cables (1010), and a transmitter (1002A) includes the result of that determination with the data that it sends to the other end if the link so that devices at the other end of the link can be caused to log off in response to extended lapses in synchronism at the first end. Each transmitter also sends an error count to the other end, and is responsive to a mode signal from the other end to reduce its signal power, so that maintenance personnel can perform many testing and diagnostic procedures from a single end of the link.

Abstract: A data coding method for digital communication systems is disclosed. In two embodiments, every four bits of data in a first data channel are mapped to a five bit code symbol. The five bit code symbols are chosen to have a duty cycle of 40 to 60 percent. In the first embodiment, a second channel of data is optionally interleaved with the encoded first channel data by placing single bits from the second channel every sixth bit in the data stream between each five bit code symbol. A plurality of synchronizing words are each formed from other pairs of five bit code symbols, and, in the two channel embodiment, the optional two bits of data from the second channel. The synchronizing words also have a duty cycle of 40 to 60 percent, and further have the characteristic that their bit patterns can only occur where they are placed in a stream of encoded data.

Abstract: MOS circuitry conducting constant current at high voltage comprises first, second and third depletion mode MOSFETs connected in a loop, with their gates joined at the junction of the second and third MOSFETs. A control circuit is coupled to the junction of the first and second MOSFETs. The drain of an enhancement mode fourth MOSFET is connected to the junction of the second and third MOSFETs while its source remains unconnected. With high voltage applied to the junction of the first and third MOSFETs, and with the control circuit essentially nonconductive, the fourth MOSFET experiences diode breakdown, thereby acting as a high voltage source which prevents gate oxide rupture on the first, second and third MOSFETs and causing the first and second MOSFETs to become nonconductive until the control circuit is again rendered conductive.

Abstract: A room thermostatic control providing for automatic power defer, i.e. modification of load consumption of electrically energized heating and cooling systems during intervals when there is a peak load demand on the electrical supply system. During power defer ambient indoor temperature is controlled by set point adjustment to minimize discomfort, e.g. by pre-boosting, by ramped temperature deferral at controlled rates, and thereafter by ramped recovery at controlled rates to the reference, i.e. desired, temperature. The preferred embodiment has normal and night set back reference temperature potentiometers and ambient indoor temperature sensing circuits providing, respectively, analog reference and analog indoor signals. Digital set point signals are derived and compared with the analog indoor signal to actuate relays controlling operation of the heating and cooling means, e.g. compressor and auxiliary resistance heating. A circuit sensing external conditions, e.g.