Patents by Inventor Robert J. Stets

Robert J. Stets has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9110975
    Abstract: Systems, methods and computer program products for generalizing a user-submitted query by forming one or more variants of the user-submitted query to generate one or more other queries, each of the one or more other queries being different from the user-submitted query. A generalized quality of result statistic is derived for a first document from respective data associated with each of the other queries, each respective data being indicative of user behavior relative to the first document as a search result for the associated other query. The generalized quality of result statistic is provided as the quality of result statistic input to a document ranking process for the first document and the user-submitted query.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: August 18, 2015
    Assignee: Google Inc.
    Inventors: Michelangelo Diligenti, Hyung-Jin Kim, Robert J. Stets, Jr.
  • Patent number: 9092510
    Abstract: In general, the subject matter described in this specification can be embodied in a method that includes: obtaining user feedback associated with quality of an electronic document; adjusting a measure of relevance for the electronic document based on a temporal element of the user feedback; and outputting the measure of relevance to a ranking engine for ranking of search results, including the electronic document, for a search for which the electronic document is returned. Obtaining the user feedback can include receiving user selections of documents presented by a document search service, the method can include evaluating the user selections in accordance with an implicit user feedback model to determine the measure of relevance, and adjusting the measure of relevance can include adjusting the measure of relevance in accordance with the implicit user feedback model.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: July 28, 2015
    Assignee: Google Inc.
    Inventors: Robert J. Stets, Jr., Mark Andrew Paskin
  • Patent number: 8788336
    Abstract: An advertiser may be provided with fast and accurate estimates of the future cost and/or performance information for one or more actual or hypothetical ads (generally referred to as “proto-ads”). Past auction information may be used to simulate auctions that the proto-ad would have competed in. The proto-ad may then participate in a “replay” of such past auctions.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: July 22, 2014
    Assignee: Google Inc.
    Inventors: Arash Baratloo, Monika H. Henzinger, Ming-Yee Iu, Wilburt Labio, Zhe Qian, Keith Randall, Robert J. Stets
  • Patent number: 8452656
    Abstract: Ads are reviewed manually once they have reached a certain expected revenue threshold (instead of attempting to review manually all incoming ads as was done in the past). This review process considers the fact that the many advertisers submit hundreds or even thousands of ads with each individually returning relatively little revenue. Such a review process should greatly reduce the number of ads, or at least to prioritize the order of ads, pending manual approval. The threshold may be set to the approximate cost of manually approving an ad, thereby reducing ad reviews pending manual review significantly. A classification of the ad (e.g., forbidden, suspicious, unchecked, an ad category, etc.), which may be determined by automated means for example, may also be used when prioritizing the order of ads pending manual approval. Revenue-based scores may also be used to control a review of an advertisement. For example, such scores may be used to select one of a plurality of review protocols.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: May 28, 2013
    Assignee: Google Inc.
    Inventors: Dipchand Nishar, Robert J. Stets
  • Patent number: 8423413
    Abstract: An advertisement for use with an online ad serving system may be automatically checked for compliance with one or more policies of the online ad serving system. If the advertisement is approved, then it is allowed by be served by the ad serving system. Follow up checks of the advertisement may be scheduled. One follow up check may be to test a landing page of the advertisement for compliance with policies. If the advertisement is not approved, hints for making the ad comply with one or more violated policies may be provided to an advertiser associated with the ad, and/or an ad serving system customer service representative. Determining whether or not to approve the advertisement may include determining violations of one or more policies by the advertisement, and, for each of the violations, determining whether or not to exempt the violation.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: April 16, 2013
    Assignee: Google Inc.
    Inventors: Gregory Joseph Badros, Robert J. Stets, Lucy Zhang
  • Patent number: 7810097
    Abstract: An information system that includes mechanisms for assigning incoming access transactions to individual access subsystems based on an analysis of the incoming access transactions. The analysis and assignment of the incoming access transactions may be used to minimize loss of cached data during power reduction in an information system.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: October 5, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert N. Mayo, Parthasarathy Ranganathan, Robert J. Stets, Jr., Deborah A. Wallach
  • Patent number: 7774796
    Abstract: Methods of factoring operating system functions into one or more groups of functions are described. Factorization permits operating systems that are not configured to support computing in an object-oriented environment to be used in an object oriented environment. This promotes distributed computing by enabling operating system resources to be instantiated and used across process and machine boundaries. In one embodiment, criteria are defined that govern how functions of an operating system are to be factored into one or more groups. Based on the defined criteria, the functions are factors into groups and groups of functions are then associated with programming objects that have data and methods, wherein the methods correspond to the operating system functions. Applications can call methods on the programming objects either directly or indirectly that, in turn, call operating system functions.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: August 10, 2010
    Assignee: Microsoft Corporation
    Inventors: Galen C. Hunt, Gerald Cermak, Robert J. Stets, Jr.
  • Patent number: 7739694
    Abstract: Methods of factoring operating system functions into one or more groups of functions are described. Factorization permits operating systems that are not configured to support computing in an object-oriented environment to be used in an object oriented environment. This promotes distributed computing by enabling operating system resources to be instantiated and used across process and machine boundaries. In one embodiment, criteria are defined that govern how functions of an operating system are to be factored into one or more groups. Based on the defined criteria, the functions are factors into groups and groups of functions are when associated with programming objects that have data and methods, wherein the methods correspond to the operating system functions. Applications can call methods on the programming objects either directly or indirectly that, in turn, call operating system functions.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: June 15, 2010
    Assignee: Microsoft Corporation
    Inventors: Galen C. Hunt, Gerald Cermak, Robert J. Stets
  • Patent number: 7681207
    Abstract: Methods of factoring operating system functions into one or more groups of functions are described. Factorization permits operating systems that are not configured to support computing in an object-oriented environment to be used in an object oriented environment. This promotes distributed computing by enabling operating system resources to be instantiated and used across process and machine boundaries. In one embodiment, criteria are defined that govern how functions of an operating system are to be factored into one or more groups. Based on the defined criteria, the functions are factors into groups and groups of functions are then associated with programming objects that have data and methods, wherein the methods correspond to the operating system functions. Applications can call methods on the programming objects either directly or indirectly that, in turn, call operating system functions.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: March 16, 2010
    Assignee: Microsoft Corporation
    Inventors: Galen C. Hunt, Gerald Cermak, Robert J. Stets, Jr.
  • Patent number: 7546475
    Abstract: A data center is disclosed with power-aware adaptation that minimizes the performance impact of reducing the power consumption of individual nodes in the data center. A data center according to the present techniques includes a request redirector that obtains an access request for data stored on a set of storage devices and that distributes the access request to one of a set of access nodes in response to a priority of the access request and a rank of each access node. A data center according to the present techniques also includes a power manager that performs a power adaptation in the data center by selecting access nodes for power reduction based on the ranks of the access nodes. The judicious distribution of access requests to appropriately ranked nodes and the judicious selection of access nodes for power reduction enhances the likelihood that higher priority cached data is not lost during power adaptation.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: June 9, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert N. Mayo, Parthasarathy Ranganathan, Robert J. Stets, Jr., Deborah A. Wallach
  • Patent number: 7389389
    Abstract: A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory line of information stored in the local memory subsystem. The directory entry includes an identification field for identifying sharer nodes that potentially cache the memory line of information. The identification field has a plurality of bits at associated positions within the identification field. Each respective bit of the identification field is associated with one or more nodes. The protocol engine furthermore sets each bit in the identification field for which the memory line is cached in at least one of the associated nodes.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: June 17, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kourosh Gharachorloo, Luiz A. Barroso, Robert J. Stets, Jr., Mosur K. Ravishankar, Andreas Nowatzyk
  • Patent number: 7334235
    Abstract: Operating system functions are defined as objects that are collections of data and methods. The objects represent operating system resources. The resource objects can be instantiated and used across process and machine boundaries. Each object has an associated handle that is stored in its private state. When an application requests a resource, it is given a second handle or pseudo handle that corresponds with the handle in the object's private state. The second handle is valid across process and machine boundaries and all access to the object takes place through the second handle. This greatly facilitates remote computing. In preferred embodiments, the objects are COM objects and remote computing is facilitated through the use of Distributed COM (DCOM) techniques. Other embodiments of the invention provide legacy and versioning support by identifying each resource, rather than the overall operating system, with a unique identifier that can specified by an application.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: February 19, 2008
    Assignee: Microsoft Corporation
    Inventors: Galen C. Hunt, Gerald Cermak, Robert J. Stets, Jr.
  • Patent number: 7003640
    Abstract: An information server with power-aware adaptation that enables power reduction while minimizing the performance impact of power reduction. An information server according to the present techniques includes a transaction prioritizer that determines which of a set of memory subsystems in the information server is to cache a set of data associated with each incoming information access transaction and further includes a power manager that performs a power adaptation in the information server in response to a set of ranks assigned to the memory subsystems. An association of priorities of the incoming information access transactions to appropriately ranked memory subsystems and the judicious selection of memory subsystems for power adaptation enhances the likelihood that higher priority cached data is not lost during power adaptation.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: February 21, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert N. Mayo, Parthasarathy Ranganathan, Robert J. Stets, Jr., Deborah A. Wallach
  • Patent number: 6925537
    Abstract: A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: August 2, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Luiz A. Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Mosur K. Ravishankar, Robert J. Stets, Jr.
  • Patent number: 6826760
    Abstract: Methods of factoring operating system functions into one or more groups of functions are described. Factorization permits operating systems that are not configured to support computing in an object-oriented environment to be used in an object oriented environment. This promotes distributed computing by enabling operating system resources to be instantiated and used across process and machine boundaries. In one embodiment, criteria are defined that govern how functions of an operating system are to be factored into one or more groups. Based on the defined criteria, the functions are factors into groups and groups of functions are then associated with programming objects that have data and methods, wherein the methods correspond to the operating system functions. Applications can call methods on the programming objects either directly or indirectly that, in turn, call operating system functions.
    Type: Grant
    Filed: June 16, 1999
    Date of Patent: November 30, 2004
    Assignee: Microsoft Corporation
    Inventors: Galen C. Hunt, Gerald Cermak, Robert J. Stets, Jr.
  • Publication number: 20040230848
    Abstract: A data center is disclosed with power-aware adaptation that minimizes the performance impact of reducing the power consumption of individual nodes in the data center. A data center according to the present techniques includes a request redirector that obtains an access request for data stored on a set of storage devices and that distributes the access request to one of a set of access nodes in response to a priority of the access request and a rank of each access node. A data center according to the present techniques also includes a power manager that performs a power adaptation in the data center by selecting access nodes for power reduction based on the ranks of the access nodes. The judicious distribution of access requests to appropriately ranked nodes and the judicious selection of access nodes for power reduction enhances the likelihood that higher priority cached data is not lost during power adaptation.
    Type: Application
    Filed: May 13, 2003
    Publication date: November 18, 2004
    Inventors: Robert N. Mayo, Parthasarathy Ranganathan, Robert J. Stets, Deborah A. Wallach
  • Publication number: 20040148472
    Abstract: A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.
    Type: Application
    Filed: October 31, 2003
    Publication date: July 29, 2004
    Inventors: Luiz A. Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Mosur K. Ravishankar, Robert J. Stets
  • Patent number: 6751710
    Abstract: The present invention relates generally to multiprocessor computer system, and particularly to a multiprocessor system designed to be highly scalable, using efficient cache coherence logic and methodologies. More specifically, the present invention is a system and method including a plurality of processor nodes configured to execute a cache coherence protocol that avoids the use of negative acknowledgment messages (NAKs) and ordering requirements on the underlying transaction-message interconnect/network and services most 3-hop transactions with only a single visit to the home node.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: June 15, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kourosh Gharachorloo, Luiz A. Barroso, Mosur K. Ravishankar, Robert J. Stets, Jr., Daniel J. Scales
  • Patent number: 6751720
    Abstract: L1 cache synonyms in a two-level cache system are detected and resolved by logic in the L2 cache. Duplicate copies of the L1 cache tags and state (“Dtags”) are maintained in the L2 cache. After a miss occurs in the L1 cache, the Dtags in the second-level cache that correspond to all possible synonym locations in the L1 cache are searched for synonyms. If a synonym is found, the L2 cache notifies the L1 cache where the requested cache line can be found in the L1 cache. The L1 cache then copies the cache line from the location where the synonym was found to the location where the miss occurred, and it invalidates the cache line at the original location. The Dtags in the second-level cache are updated to reflect the changes made in the L1 cache.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: June 15, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Luiz André Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Robert J. Stets, Jr., Mosur Kumaraswamy Ravishankar
  • Patent number: 6748498
    Abstract: A system including a plurality of processor nodes is configured to execute a cache coherence protocol that avoids the use of negative acknowledgments and ordering requirements on the underlying transaction-message interconnect/network, and implements store-conditional memory transactions. A store-conditional memory transaction succeeds if a directory tracking the state of a memory line of information unambiguously indicates that the requesting node is the exclusive owner of the memory line, if the directory ambiguously indicates that the requesting node is sharing the memory line and the requesting node is in fact sharing the memory line, or if the directory unambiguously indicates that the requesting node is sharing the memory line.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: June 8, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Kourosh Gharachorloo, Luiz Andre Barroso, Mosur K. Ravishankar, Robert J. Stets, Daniel J. Scales