Abstract: In a processing system, a conversion circuit coupled to a system bus generates a flow control unit (FLIT) and provides the FLIT to a link interface circuit for transmission over an external link. The external link may be a peripheral component interface (PCI) express (PCIe) link coupled to an external device comprising a cache or memory. The conversion circuit generates the FLIT, including write information based on the write instruction, metadata associated with at least one cache line, and cache line chunks, including bytes of a cache line. The cache line chunks may be chunks of one of the at least one cache line. Including the metadata in the FLIT avoids separately transmitting the at least one cache line and the metadata over the external link, which improves performance compared to generating separate transmissions. In some examples, the FLIT corresponds to a compute express link (CXL) protocol FLIT.

Abstract: In a processing system, a conversion circuit coupled to a system bus generates a flow control unit (FLIT) and provides the FLIT to a link interface circuit for transmission over an external link. The external link may be a peripheral component interface (PCI) express (PCIe) link coupled to an external device comprising a cache or memory. The conversion circuit generates the FLIT, including write information based on the write instruction, metadata associated with at least one cache line, and cache line chunks, including bytes of a cache line. The cache line chunks may be chunks of one of the at least one cache line. Including the metadata in the FLIT avoids separately transmitting the at least one cache line and the metadata over the external link, which improves performance compared to generating separate transmissions. In some examples, the FLIT corresponds to a compute express link (CXL) protocol FLIT.

Abstract: The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.

Abstract: In a processing system, a conversion circuit coupled to a system bus generates a flow control unit (FLIT) and provides the FLIT to a link interface circuit for transmission over an external link. The external link may be a peripheral component interface (PCI) express (PCIe) link coupled to an external device comprising a cache or memory. The conversion circuit generates the FLIT, including write information based on the write instruction, metadata associated with at least one cache line, and cache line chunks, including bytes of a cache line. The cache line chunks may be chunks of one of the at least one cache line. Including the metadata in the FLIT avoids separately transmitting the at least one cache line and the metadata over the external link, which improves performance compared to generating separate transmissions. In some examples, the FLIT corresponds to a compute express link (CXL) protocol FLIT.

Abstract: The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.

Abstract: A system-on-a-chip (SoC) with one or more processors and other system components may have one or more peripheral component interconnect express (PCIe) physical connections between the processors and other system components to provide agent-to-agent communication. The agents on the communication fabric of the SoC may transmit data through the hardware PCIe interface where a transmitter device of an agent or digital logic component receives at least one data block for transmission and receives a flag corresponding to the at least one data block. The transmitter device may then send, via a PCIe physical layer, the received data blocks as a payload of a packet based on the flag, where the packet has a PCIe compliant header. The payload of the packet with the PCIe header may be entirely composed of these data blocks or flits from the agent.

Abstract: Apparatuses, systems, and methods for implied sequence numbering of transactions in a processor-based system. The processor-based system includes a transmit circuit configured to generate an implied sequence number for each entry to be transmitted as a packet. The transmit circuit is configured to generate a packet to be transmitted based on an entry, wherein the packet including the payload information and the transmit check value based on the implied sequence number and associated with the entry. In this manner, including an individual sequence number with every transmitted packet may be reduced or avoided to reduce or avoid consuming bandwidth on the communications interface, as the bits used by the sequence number could ordinarily be used for data transmission instead. A receiver circuit is configured to receive the transmitted packet including the payload and the transmit check value, wherein the transmit check value is based on the transmit sequence number.

Abstract: The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.

Abstract: Providing multi-socket memory coherency using cross-socket snoop filtering in processor-based systems is disclosed. In this regard, a processor-based system provides a plurality of processor sockets, each associated with a coherency directory including a plurality of coherency directory entries each storing status indicators corresponding to memory granules of a local memory hierarchy. A point of serialization (POS) circuit of the processor-based system receives a memory access request including a local memory address, and retrieves a coherency directory entry corresponding to the local memory address. If a status indicator of the coherency directory entry corresponding to a memory granule associated with the local memory address indicates that a remote snoop is required, the POS circuit performs the remote snoop of one or more remote processor sockets indicated by the status indicator. If not, the POS circuit returns data from the local memory hierarchy for the memory access request.

Abstract: The invention provides a perceptually-based system for pattern retrieval and matching, suitable for use in a wide variety of information processing applications. An illustrative embodiment of the system uses a predetermined vocabulary comprising one or more dimensions to extract color and texture information from an information signal, e.g., an image, selected by a user. The system then generates a distance measure characterizing the relationship of the selected image to another image stored in a database, by applying a grammar, comprising a set of predetermined rules, to the color and texture information extracted from the selected image and corresponding color and texture information associated with the stored image. The vocabulary may include dimensions such as overall color, directionality and orientation, regularity and placement, color purity, and pattern complexity and heaviness.

Abstract: The invention provides a perceptually-based system for pattern retrieval and matching, suitable for use in a wide variety of information processing applications. An illustrative embodiment of the system uses a predetermined vocabulary comprising one or more dimensions to extract color and texture information from an information signal, e.g., an image, selected by a user. The system then generates a distance measure characterizing the relationship of the selected image to another image stored in a database, by applying a grammar, comprising a set of predetermined rules, to the color and texture information extracted from the selected image and corresponding color and texture information associated with the stored image. The vocabulary may include dimensions such as overall color, directionality and orientation, regularity and placement, color purity, and pattern complexity and heaviness.

Abstract: The invention provides a perceptually-based system for pattern retrieval and matching, suitable for use in a wide variety of information processing applications. An illustrative embodiment of the system uses a predetermined vocabulary comprising one or more dimensions to extract color and texture information from an information signal, e.g., an image, selected by a user. The system then generates a distance measure characterizing the relationship of the selected image to another image stored in a database, by applying a grammar, comprising a set of predetermined rules, to the color and texture information extracted from the selected image and corresponding color and texture information associated with the stored image. The vocabulary may include dimensions such as overall color, directionality and orientation, regularity and placement, color purity, and pattern complexity and heaviness.

Abstract: The invention provides a perceptually-based system for pattern retrieval and matching, suitable for use in a wide variety of information processing applications. An illustrative embodiment of the system uses a predetermined vocabulary comprising one or more dimensions to extract color and texture information from an information signal, e.g., an image, selected by a user. The system then generates a distance measure characterizing the relationship of the selected image to another image stored in a database, by applying a grammar, comprising a set of predetermined rules, to the color and texture information extracted from the selected image and corresponding color and texture information associated with the stored image. The vocabulary may include dimensions such as overall color, directionality and orientation, regularity and placement, color purity, and pattern complexity and heaviness.

Abstract: The invention provides a perceptually-based system for pattern retrieval and matching, suitable for use in a wide variety of information processing applications. An illustrative embodiment of the system uses a predetermined vocabulary comprising one or more dimensions to extract color and texture information from an information signal, e.g., an image, selected by a user. The system then generates a distance measure characterizing the relationship of the selected image to another image stored in a database, by applying a grammar, comprising a set of predetermined rules, to the color and texture information extracted from the selected image and corresponding color and texture information associated with the stored image. The vocabulary may include dimensions such as overall color, directionality and orientation, regularity and placement, color purity, and pattern complexity and heaviness.

Abstract: A method of encoding a video sequence including a sequence of video images includes first comparing elements of a portion of a first video image (e.g., pixels of a macroblock of a current frame) with elements of a portion of a second video image (e.g., corresponding pixels of a macroblock of a previous frame) to generate respective intensity difference values for the element comparisons. Then, a first value (e.g., one) is assigned to the intensity difference values that are above a visually perceptible threshold value and a second value (e.g., zero) is assigned to the intensity difference values that are at or below the visually perceptible threshold value. Next, the method includes summing the first and second values to generate a sum. If the sum is greater than a predetermined decision value, the portion of the first video image is encoded (e.g., motion compensated). The method is fully compatible and, thus, may be implemented with video standards such as, for example, H.261, H.

Abstract: An image-processing system for perceptual coding of an image is disclosed. Coding is accomplished through an analysis of human visual sensitivity to noise in halftone images and an analysis of one or more signals representing the image to be coded. These analyses determine levels of noise. A first image is encoded so as to produce encoded values without introducing noise which exceeds a determined level of noise. Analysis of human visual sensitivity is carried out under a set of user determined conditions comprising viewing distance and lighting. The encoded image is communicated and decoded to produce representation of the first image for display. As part of displaying the representation of the first image, a halftoning process is carried out. The halftoning process may comprise the interpolation of data values of the representation of the first image as well as the addition of micro-dither to the representation.

Abstract: Method and apparatus are disclosed for deinterlacing of an interlaced video frame sequence using interpolation estimations, such as spatial and temporal interpolations. Interpolations requiring a less accurate estimation of missing pixel values in the frames being deinterlaced, such that an interpolation may be performed with a minimum of error, are performed before interpolations which require a more accurate estimation of missing pixel values for performing an interpolation, such that estimates of missing pixel values are obtained with a minimum of error. Interpolation estimations are weighted in combination for computing approximations of missing pixel values in accordance with the errors associated with the respective interpolations.