Patents by Inventor Robert Joersz
Robert Joersz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8589656Abstract: Queuing of received transactions that have a resource conflict is disclosed. A first node receives a first transaction from a second node, where the first transaction relates to a resource of the first node. The transaction may be a request relating to a memory line of the first node, for instance. It is determined that a second transaction that relates to this resource of the first node is already being processed by the first node. Therefore, the first transaction is enqueued in a conflict queue within the first node. The queuing may be a linked list, a priority queue, or another type of queue. Once the second transaction has been processed, the first transaction is restarted for processing by the first node. The first transaction is then processed by the first node.Type: GrantFiled: June 25, 2011Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Donald R. DeSota, Robert Joersz, Davis A. Miller, Maged M. Michael
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Patent number: 8578130Abstract: Partitioning a node of a multi-node system into more than one partition is disclosed. First resources of the node are physically partitioned into more than one partition. The first resources physically partitioned to each partition are directly inaccessible by other partitions of the node. Second resources of the node are then internally logically partitioned into the more than one partition. Each second resource internally separates transactions of one partition from transactions of other partitions. Furthermore, the node can be dynamically repartitioned into other partitions, such as a single partition, without having to take the multi-node system down. Operating system (OS) instances of the partitions may have assumptions provided to allow for dynamic partitioning, such as quiescing the processors and/or the input/output components being reconfigured, purging remote cache entries across the entire OS, etc.Type: GrantFiled: March 10, 2003Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Donald R. DeSota, Bruce M. Gilbert, Robert Joersz, Wayne A. Downer
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Publication number: 20110258401Abstract: Queuing of received transactions that have a resource conflict is disclosed. A first node receives a first transaction from a second node, where the first transaction relates to a resource of the first node. The transaction may be a request relating to a memory line of the first node, for instance. It is determined that a second transaction that relates to this resource of the first node is already being processed by the first node. Therefore, the first transaction is enqueued in a conflict queue within the first node. The queuing may be a linked list, a priority queue, or another type of queue. Once the second transaction has been processed, the first transaction is restarted for processing by the first node. The first transaction is then processed by the first node.Type: ApplicationFiled: June 25, 2011Publication date: October 20, 2011Inventors: Donald R. DeSota, Robert Joersz, Davis A. Miller, Maged M. Michael
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Patent number: 8015248Abstract: Queuing of received transactions that have a resource conflict is disclosed. A first node receives a first transaction from a second node, where the first transaction relates to a resource of the first node. The transaction may be a request relating to a memory line of the first node, for instance. It is determined that a second transaction that relates to this resource of the first node is already being processed by the first node. Therefore, the first transaction is enqueued in a conflict queue within the first node. The queuing may be a linked list, a priority queue, or another type of queue. Once the second transaction has been processed, the first transaction is restarted for processing by the first node. The first transaction is then processed by the first node.Type: GrantFiled: March 29, 2009Date of Patent: September 6, 2011Assignee: International Business Machines CorporationInventors: Donald R. DeSota, Robert Joersz, Davis A. Miller, Maged M. Michael
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Patent number: 7827449Abstract: Non-inline transaction error correction is disclosed. Where a transaction being processed in a pipeline is determined to include a correctable error, it is output, or drained, from the pipeline into an error queue. The pipeline is switched from a normal mode of operation to a correction mode of operation. In the correction mode, a correction command is inserted into and processed within the pipeline to correct the error within the transaction. The pipeline is switched from the correction mode of operation to a restart mode of operation. In the restart mode, the transaction is reprocessed within the pipeline. The pipeline is then switched from the restart mode of operation back to the normal mode of operation.Type: GrantFiled: January 27, 2008Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Bruce M. Gilbert, Donald R. DeSota, Robert Joersz
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Patent number: 7594080Abstract: The temporary storage of a memory line to be stored in a cache while waiting for another memory line to be evicted from the cache is disclosed. A method includes evicting a first memory line currently stored in the cache and storing a second memory line not currently stored in the cache in its place. While the first memory line is being evicted, such as by first being inserted into an eviction queue, the second memory line is temporarily stored in a buffer. The buffer may be a data transfer buffer (DTB). Upon eviction of the first memory line, the second memory line is moved from the buffer into the cache.Type: GrantFiled: September 12, 2003Date of Patent: September 22, 2009Assignee: International Business Machines CorporationInventors: Thomas D. Lovett, Maged M. Michael, Robert Joersz, Donald R. DeSota
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Publication number: 20090187628Abstract: Queuing of received transactions that have a resource conflict is disclosed. A first node receives a first transaction from a second node, where the first transaction relates to a resource of the first node. The transaction may be a request relating to a memory line of the first node, for instance. It is determined that a second transaction that relates to this resource of the first node is already being processed by the first node. Therefore, the first transaction is enqueued in a conflict queue within the first node. The queuing may be a linked list, a priority queue, or another type of queue. Once the second transaction has been processed, the first transaction is restarted for processing by the first node. The first transaction is then processed by the first node.Type: ApplicationFiled: March 29, 2009Publication date: July 23, 2009Inventors: Donald R. DeSota, Robert Joersz, Davis A. Miller, Maged M. Michael
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Patent number: 7529800Abstract: A method of queuing of received transactions that have a resource conflict is disclosed. A first node receives a first transaction from a second node, where the first transaction relates to a resource of the first node. The transaction may be a request relating to a memory line of the first node, for instance. It is determined that a second transaction that relates to this resource of the first node is already being processed by the first node. Therefore, the first transaction is enqueued in a conflict queue within the first node. The queuing may be a linked list, a priority queue, or another type of queue. Once the second transaction has been processed, the first transaction is restarted for processing by the first node. The first transaction is then processed by the first node.Type: GrantFiled: December 18, 2003Date of Patent: May 5, 2009Assignee: International Business Machines CorporationInventors: Donald R. DeSota, Robert Joersz, Davis A. Miller, Maged M. Michael
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Publication number: 20080141078Abstract: Non-inline transaction error correction is disclosed. Where a transaction being processed in a pipeline is determined to include a correctable error, it is output, or drained, from the pipeline into an error queue. The pipeline is switched from a normal mode of operation to a correction mode of operation. In the correction mode, a correction command is inserted into and processed within the pipeline to correct the error within the transaction. The pipeline is switched from the correction mode of operation to a restart mode of operation. In the restart mode, the transaction is reprocessed within the pipeline. The pipeline is then switched from the restart mode of operation back to the normal mode of operation.Type: ApplicationFiled: January 27, 2008Publication date: June 12, 2008Inventors: Bruce M. Gilbert, Donald R. DeSota, Robert Joersz
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Patent number: 7383464Abstract: Non-inline transaction error correction is disclosed. Where a transaction being processed in a pipeline is determined to include a correctable error, it is output, or drained, from the pipeline into an error queue. The pipeline is switched from a normal mode of operation to a correction mode of operation. In the correction mode, a correction command is inserted into and processed within the pipeline to correct the error within the transaction. The pipeline is switched from the correction mode of operation to a restart mode of operation. In the restart mode, the transaction is reprocessed within the pipeline. The pipeline is then switched from the restart mode of operation back to the normal mode of operation.Type: GrantFiled: December 8, 2003Date of Patent: June 3, 2008Assignee: International Business Machines CorporationInventors: Bruce M. Gilbert, Donald R. DeSota, Robert Joersz
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Patent number: 7210018Abstract: A multiple-stage pipeline for transaction conversion is disclosed. A method is disclosed that converts a transaction into a set of concurrently performable actions. In a first pipeline stage, the transaction is decoded into an internal protocol evaluation (PE) command, such as by utilizing a look-up table (LUT). In a second pipeline stage, an entry within a PE random access memory (RAM) is selected, based on the internal PE command. This may be accomplished by converting the internal PE command into a PE RAM base address and an associated qualifier thereof. In a third pipeline stage, the entry within the PE RAM is converted to the set of concurrently performable actions, such as based on the PE RAM base address and its associate qualifier.Type: GrantFiled: December 30, 2002Date of Patent: April 24, 2007Assignee: International Business Machines CorporationInventors: Donald R. DeSota, Bruce M. Gilbert, Robert Joersz, Thomas D. Lovett, Maged M. Michael
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Patent number: 7089372Abstract: Information regarding memory access by other nodes within a coherency controller of a node is locally stored. The coherency controller receives a transaction relating a line of local memory of the node. In response to locally determining that the line of the local memory is not being cached by another node and/or has not been modified by another node, the coherency controller processes the transaction without accessing tag directory information regarding the line. A table within the controller may store entries corresponding to local memory sections. Each entry includes a count value tracking a number of lines of the section being cached by other nodes, and a count value tracking a number of lines of the section that have been modified by other nodes. The table may also include flags corresponding to the sections, each flag indicating the validity of the section's contents.Type: GrantFiled: December 1, 2003Date of Patent: August 8, 2006Assignee: International Business Machines CorporationInventors: Donald R. DeSota, William Durr, Robert Joersz, Davis A. Miller
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Patent number: 7000089Abstract: The assignment of an address to a transaction for serialization purposes is disclosed. A simulated address is assigned to a transaction of a first type. The simulated address may be determined by selecting a mask based on one or more bits of a command type attribute of the transaction, and performing a logical OR operation on the highest bits of the mask with a number of bits determined by concatenating various bits of various attributes of the transaction. The lowest bits of the resulting simulated address can be incremented for each transaction assigned a simulated address having the same highest bits. The transaction is serialized relative to other transactions of the first type, such as I/O-related transactions, utilizing a serialization approach for transactions of a second type. The serialization approach may be an existing approach already used to serialize transactions of the second type, such as coherent transactions.Type: GrantFiled: December 20, 2002Date of Patent: February 14, 2006Assignee: International Business Machines CorporationInventors: William Durr, Bruce M. Gilbert, Robert Joersz
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Patent number: 6996665Abstract: A hazard queue for a pipeline, such as a multiple-stage pipeline for transaction conversion, is disclosed. A transaction in the pipeline is determined to represent a hazard relative to another transaction, such as by evaluating the transaction against a hazard content-addressable memory (CAM). The hazard CAM can enforce various hazard rules, such as considering a transaction as active if it is referencing a memory line and is currently being processed within the pipeline, and ensuring that only one active transaction with a given coherent memory line is in the pipeline at a single time. In response to determining that a transaction is a hazard, the transaction is routed to a hazard queue, such as at the end of the pipeline. Once the hazard is released, the transaction re-enters the pipeline.Type: GrantFiled: December 30, 2002Date of Patent: February 7, 2006Assignee: International Business Machines CorporationInventors: Donald R. DeSota, Bruce M. Gilbert, Robert Joersz, Eric N. Lais, Maged M. Michael
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Publication number: 20050149603Abstract: A method of queuing of received transactions that have a resource conflict is disclosed. A first node receives a first transaction from a second node, where the first transaction relates to a resource of the first node. The transaction may be a request relating to a memory line of the first node, for instance. It is determined that a second transaction that relates to this resource of the first node is already being processed by the first node. Therefore, the first transaction is enqueued in a conflict queue within the first node. The queuing may be a linked list, a priority queue, or another type of queue. Once the second transaction has been processed, the first transaction is restarted for processing by the first node. The first transaction is then processed by the first node.Type: ApplicationFiled: December 18, 2003Publication date: July 7, 2005Inventors: Donald DeSota, Robert Joersz, Davis Miller, Maged Michael
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Publication number: 20050125695Abstract: Non-inline transaction error correction is disclosed. Where a transaction being processed in a pipeline is determined to include a correctable error, it is output, or drained, from the pipeline into an error queue. The pipeline is switched from a normal mode of operation to a correction mode of operation. In the correction mode, a correction command is inserted into and processed within the pipeline to correct the error within the transaction. The pipeline is switched from the correction mode of operation to a restart mode of operation. In the restart mode, the transaction is reprocessed within the pipeline. The pipeline is then switched from the restart mode of operation back to the normal mode of operation.Type: ApplicationFiled: December 8, 2003Publication date: June 9, 2005Inventors: Bruce Gilbert, Donald DeSota, Robert Joersz
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Publication number: 20050120183Abstract: The local storage of information regarding memory access by other nodes within a coherency controller of a node is disclosed. The coherency controller receives a transaction relating a line of local memory of the node. In response to locally determining that the line of the local memory is not being cached by another node and/or has not been modified by another node, the coherency controller processes the transaction without accessing tag directory information regarding the line. A table within the controller may store entries corresponding to local memory sections. Each entry includes a count value tracking a number of lines of the section being cached by other nodes, and a count value tracking a number of lines of the section that have been modified by other nodes. The table may also include flags corresponding to the sections, each flag indicating the validity of the section's contents.Type: ApplicationFiled: December 1, 2003Publication date: June 2, 2005Inventors: Donald DeSota, William Durr, Robert Joersz, Davis Miller
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Publication number: 20050060383Abstract: The temporary storage of a memory line to be stored in a cache while waiting for another memory line to be evicted from the cache is disclosed. A method includes evicting a first memory line currently stored in the cache and storing a second memory line not currently stored in the cache in its place. While the first memory line is being evicted, such as by first being inserted into an eviction queue, the second memory line is temporarily stored in a buffer. The buffer may be a data transfer buffer (DTB). Upon eviction of the first memory line, the second memory line is moved from the buffer into the cache.Type: ApplicationFiled: September 12, 2003Publication date: March 17, 2005Inventors: Thomas Lovett, Maged Michael, Robert Joersz, Donald DeSota
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Publication number: 20040181647Abstract: Partitioning a node of a multi-node system into more than one partition is disclosed. First resources of the node are physically partitioned into more than one partition. The first resources physically partitioned to each partition are directly inaccessible by other partitions of the node. Second resources of the node are then internally logically partitioned into the more than one partition. Each second resource internally separates transactions of one partition from transactions of other partitions. Furthermore, the node can be dynamically repartitioned into other partitions, such as a single partition, without having to take the multi-node system down. Operating system (OS) instances of the partitions may have assumptions provided to allow for dynamic partitioning, such as quiescing the processors and/or the input/output components being reconfigured, purging remote cache entries across the entire OS, etc.Type: ApplicationFiled: March 10, 2003Publication date: September 16, 2004Applicant: International Business Machines CorporationInventors: Donald R. DeSota, Bruce M. Gilbert, Robert Joersz
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Publication number: 20040128462Abstract: A multiple-stage pipeline for transaction conversion is disclosed. A method is disclosed that converts a transaction into a set of concurrently performable actions. In a first pipeline stage, the transaction is decoded into an internal protocol evaluation (PE) command, such as by utilizing a look-up table (LUT). In a second pipeline stage, an entry within a PE random access memory (RAM) is selected, based on the internal PE command. This may be accomplished by converting the internal PE command into a PE RAM base address and an associated qualifier thereof. In a third pipeline stage, the entry within the PE RAM is converted to the set of concurrently performable actions, such as based on the PE RAM base address and its associate qualifier.Type: ApplicationFiled: December 30, 2002Publication date: July 1, 2004Inventors: Donald R. DeSota, Bruce M. Gilbert, Robert Joersz, Thomas D. Lovett, Maged M. Michael