Abstract: In a phase-locked loop (PLL) calibration system and method, the PLL input reference clock is phase-modulated, the resulting PLL output modulation is measured, and PLL calibration signals, such as a PLL proportional path adjustment signal and a PLL integral path adjustment signal, are derived from the measured PLL output modulation.

Abstract: A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.

Abstract: In a phase-locked loop (PLL) calibration system and method, the PLL input reference clock is phase-modulated, the resulting PLL output modulation is measured, and PLL calibration signals, such as a PLL proportional path adjustment signal and a PLL integral path adjustment signal, are derived from the measured PLL output modulation.

Abstract: A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.

Abstract: A precision delay system allowing clock edges to be delayed with new delay values every clock period T. The internal delay elements are reprogrammed every clock cycle with reprogramming transients suppressed by clock independent blanking circuitry. The system allows the use of delay elements with a maximum delay of one-half (T/2) the clock period to continuously span a full clock cycle T delay range with full cycle-by-cycle reprogramming.

Abstract: A clock qualification circuit used to selectively enable a clock edge to transfer new delay data from a first-in-first-out (FIFO) circuit in a precision delay line circuit. The circuit qualifies the clock without generating undesirable pulses (glitches) and causing false loading of new delay data in a timing on the fly delay line implementation.

Abstract: A disk drive has a disk format that includes servo fields and interspersed data fields. The disk drive includes a timing generator for generating timing signals to synchronize and control operation of read/write and servo positioning circuits. The disk drive also includes a writable program store that stores a plurality of timing signal commands for generating timing signals in conformance with the format of a disk. A processor loads the writable program store with the timing signal commands and the processor further enables readout of those commands from the writable program store. An execution register receives the timing signal commands and generates timing signals in response, the timing signals controlling synchronization and operation of the read/write circuits. As the writable program store is reprogrammable, at will, substantial flexibility is achieved in the creation of such timing signals.

Abstract: A disk drive system employs uniform size data blocks, with each disk having a sectorized track format and each sector of a track including at least one servo burst. Data blocks exhibit a constant data density across a plurality of disk tracks of differing radii. The system comprises read/write apparatus for accessing both servo signals and data signals in each disk sector. A servo system is responsive to servo signals fed from the read/write apparatus to generate a synchronizing signal. A data sector pulse generation circuit is responsive to the synchronizing signal to generate and pass to the read/write apparatus, a data sector pulse for each block of data commencing in a sector. That data sector pulse enables operation of the read/write apparatus upon the data block. A control circuit enables the delay of generation of a next data sector pulse when any block of data is split by a servo burst. The delay period is the duration of the servo burst and the portion of the data block that follows the servo burst.