Abstract: A method for forming a through silicon via (TSV) in a substrate may include forming a dielectric layer on the substrate; forming an opening through the dielectric layer and into the substrate using a single mask over the dielectric layer; expanding the opening in the dielectric layer, undercutting the single mask, to form an expanded upper portion; removing the single mask; and filling the opening, including the expanded upper portion, with a conductor. A resulting structure may include a substrate; a dielectric layer over the substrate; and a self-aligned through silicon via (TSV) extending through the dielectric layer and the substrate.

Abstract: Pixel sensor cells with an opaque mask layer and methods of manufacturing are provided. The method includes forming a transparent layer over at least one active pixel and at least one dark pixel of a pixel sensor cell. The method further includes forming an opaque region in the transparent layer over the at least one dark pixel.

Abstract: Enhanced efficiency solar cells and methods of manufacture of such cells are described herein. In an illustrative example, the solar cell includes at least one or more collector lens bars each of which extend on sides of front contacts and positioned over a respective active area of one or more active areas in such as position as to guide light onto the one or more active areas. A protective layer covers the at least one or more collector lens bars.

Abstract: A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer.

Abstract: A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.

Abstract: Systems and methods simultaneously form first openings and second openings in a substrate. The first openings are formed smaller than the second openings. The method also simultaneously forms a first material in the first openings and the second openings. The first material fills the first openings, and the first material lines the second openings. The method forms a second material different than the first material in the second openings. The second material fills the second openings. The method forms a plurality of integrated circuit structures over the first material and the second material within the second openings. The method applies mechanical stress to the substrate to cause the substrate to split along the first openings.

Abstract: Systems for real-time contamination, environmental, or physical monitoring of a photomask. The system includes an electronics package physically mounted to the photomask and a processing device in communication with the electronics package. The electronics package includes a sensor configured to monitor the attribute and generate sensor data. The processing device is configured to analyze the sensor data communicated from the electronics package to the processing device.

Abstract: Methods, structures, and design structures for improved adhesion of protective layers of imager microlens structures are disclosed. A method of fabricating a semiconductor structure includes forming an interfacial region between a microlens and a protective oxide layer. The interfacial region has a lower concentration of oxygen than the protective oxide layer.

Abstract: A flat-top convex-bottom lower lens is formed by first applying a positive tone photoresist over a silicon oxide layer and an optional metallic barrier layer thereupon in a back-end-of-line (BEOL) metallization structure. The positive tone photoresist is exposed under defocused illumination conditions and/or employing a half-tone mask so that a cross-sectional profile of the positive tone photoresist after exposure contains a continuous and smooth concave profile, which is transferred into the underlying silicon oxide layer to form a concave cavity therein. After removing the photoresist, the cavity is filled with a high refractive index material such as silicon nitride, and planarized to form a flat-top convex-bottom lower lens. Various aluminum metal structures, a color filter, and a convex-top flat-bottom upper lens are thereafter formed so that the upper lens and the lower lens constitute a composite lens system.

Abstract: Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.

Abstract: Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.

Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.

Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.

Abstract: An apparatus for real-time contamination, environmental, or physical monitoring of a photomask. The apparatus includes a photomask having a patterned region configured to correspond to features of an integrated circuit and a sensor physically coupled with the photomask. The sensor is configured to monitor an attribute related to the photomask. Attributes monitored by the sensor may include chemical contamination, temperature changes, humidity changes, acceleration, shock, vibration, optical flux through the photomask, electrostatic discharge environment of the photomask, particulates, and pressure.

Abstract: Disclosed herein an image sensor chip, including a substrate having at least one via extending through at least one inter layer dielectric (ILD); a first conductive layer over the ILD, wherein the first conductive layer has a first thickness; a second conductive layer over the first conductive layer, wherein the second conductive layer has a second thickness of less than the first thickness; a polymer layer over the second conductive layer, the polymer layer including a cavity; a plurality of cavity components in the cavity; and an optically transparent layer contacting the polymer layer and covering the cavity.

Abstract: A structure and method for increasing the sensitivity of pixel sensors by eliminating a gap space formed between adjacent microlens structures in a pixel sensor array. Advantageously, exposure and flowing conditions are such that adjacent microlens structures touch (are webbed) at a horizontal cross-section, yet have a round lens shape in all directions. Particularly, exposure and flowing conditions are such that each touching microlens structure is formed to have a matched uniform radius of curvature at a horizontal cross-section and at a 45 degree cross-sections. To improve quality of mircrolens structure uniformity exhibited at all pixel locations including those near a pixel array edge or corner, a top anti-reflective coating layer is applied on top of a photoresist layer prior to the exposure and flowing steps.

Abstract: A structure and method for increasing the sensitivity of pixel sensors by eliminating a gap space formed between adjacent microlens structures in a pixel sensor array. Advantageously, exposure and flowing conditions are such that adjacent microlens structures touch (are webbed) at a horizontal cross-section, yet have a round lens shape in all directions. Particularly, exposure and flowing conditions are such that each touching microlens structure is formed to have a matched uniform radius of curvature at a horizontal cross-section and at a 45 degree cross-sections.

Abstract: An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract: A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.