Abstract: An apparatus for a differential redundancy multiplexor for flash memory devices. One embodiment comprises a memory array comprising a main memory element and a redundant element. A sense amp is coupled to the memory array to evaluate the main memory element and to generate a first pair of differential output signals. A redundant sense amp is coupled to the memory array. The redundant sense amp is to evaluate the redundant memory element and to generate a second pair of differential output signals. A multiplexor is coupled to the sense amp and the redundant sense amp. The multiplexor is to receive the first pair and the second pair. The multiplexor is to generate a single ended output from evaluating a single pair of differential output signals. Control logic coupled to the multiplexor to control whether the first pair or the second pair is the single pair of differential output signals evaluated.

Abstract: An apparatus and method for protecting memory blocks in a block-based flash erasable programmable read only memory device are disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register is coupled to each of the lockable blocks in the memory array. A logic state is coupled to one input of the volatile lock register, and a block set/reset line is coupled to a second input of the volatile lock register. A block latch control line is coupled to one input of the logic gate, and a group latch control line is coupled to a second input of the logic gate. The method includes reading a first command of a multi-cycle command specifying a lock configuration of one or more memory blocks and reading a second command specifying the number of memory blocks to be lock configured.

Abstract: A flash memory using a pre-sensing amplifier coupled to receive differential inputs from a pair of memory cells of said flash memory array and to generate a differential output from the pre-sensing amplifier. The differential output is coupled to a bus, which is also coupled to a post-sensing amplifier. The differential configuration on the bus allows marginal voltage differences to be detected by the post-sensing amplifier so that logic states from the flash memory can be sensed without the bus transitioning to half of the supply voltage.

Abstract: An apparatus for a differential redundancy multiplexor for flash memory devices. One embodiment comprises a memory array comprising a main memory element and a redundant element. A sense amp is coupled to the memory array to evaluate the main memory element and to generate a first pair of differential output signals. A redundant sense amp is coupled to the memory array. The redundant sense amp is to evaluate the redundant memory element and to generate a second pair of differential output signals. A multiplexor is coupled to the sense amp and the redundant sense amp. The multiplexor is to receive the first pair and the second pair. The multiplexor is to generate a single ended output from evaluating a single pair of differential output signals. Control logic coupled to the multiplexor to control whether the first pair or the second pair is the single pair of differential output signals evaluated.

Abstract: A flash memory using a pre-sensing amplifier coupled to receive differential inputs from a pair of memory cells of said flash memory array and to generate a differential output from the pre-sensing amplifier. The differential output is coupled to a bus, which is also coupled to a post-sensing amplifier. The differential configuration on the bus allows marginal voltage differences to be detected by the post-sensing amplifier so that logic states from the flash memory can be sensed without the bus transitioning to half of the supply voltage.

Abstract: A circuit for protecting memory blocks in a block-based flash EPROM device is disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register is coupled to each of the lockable blocks in the memory array. A logic gate is coupled to one input of the volatile lock register, and a block set/reset line is coupled to a second input of the volatile lock register. A block latch control line is coupled to one input of the logic gate, and a group latch control line is coupled to a second input of the logic gate.

Abstract: An embodiment of the invention is directed to a method of operating a flash memory, which includes discharging at least one local wordline of an unselected block of flash memory cells during an interval in which a selected set of flash memory cells are being conditioned, such that the at least one local wordline does not develop a charge that is sufficient to corrupt the data stored in the unselected block.

Abstract: An apparatus and method for protecting memory blocks in a block-based flash erasable programmable read only memory (EPROM) device are disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register is coupled to each of the lockable blocks in the memory array. A logic gate is coupled to one input of the volatile lock register, and a block set/reset line is coupled to a second input of the volatile lock register. A block latch control line is coupled to one input of the logic gate, and a group latch control line is coupled to a second input of the logic gate. The method includes reading a first command of a multi-cycle command specifying a lock configuration of one or more memory blocks and reading a second command specifying the number of memory blocks to be lock configured.

Abstract: A nonvolatile memory includes a global line and a first block and a second block. The first block includes a plurality of first local lines and a first local decoder coupled to the global line and the first local lines for selectively coupling the global line to one of the first local lines in accordance with an address when the first local decoder is enabled and for isolating the first local lines from the global line when the first local decoder is disabled. The second block includes a plurality of second local lines and a second local decoder coupled to the global line and the second local lines for selectively coupling the global line to one of the second local lines in accordance with the address when the second local decoder is enabled and for isolating the second local lines from the global line when the second local decoder is disabled such that interference between the first and second blocks is eliminated during memory operations.

Abstract: A method and circuitry for providing dual row selection using a multiplexed tri-level decoder is disclosed. For one embodiment, the multiplexed tri-level decoder is a 3:8 decoder, the major components of which are a buffer and 8 three input NAND circuits. The NAND circuits are peculiar in that the inputs are referenced to a VCC operational voltage supply, and the outputs are referenced to a VPX tri-level supply voltage. The output of each NAND circuit is used to select one row or word line. During preconditioning and post conditioning, the decoder is required to enable two adjacent rows: the row selected and the next row. The present design implements dual row selection by adding a pass transistor that connects the word line enable driver to the driver of the previous row within the VPX level circuitry. This is in contrast to the previous design approach of implementing dual row selection by using VCC level logic. The disclosed implementation eliminates gates in the speed path of the circuit.