Abstract: A peak voltage detector is used to detect the absolute value of the peak differential amplitude of a differential input signal. The peak voltage detector includes a differential amplifier receiving the differential input signal and generating a corresponding pair of differential output signals. The voltage detector also includes a capacitor on which an output signal is generated. A first differential comparator generates a first signal whenever the differential voltage from the differential amplifier is greater than the voltage of the output signal. A second differential comparator generates a second signal whenever the negative of the differential voltage from the differential amplifier is greater than the voltage of the output signal. A current source applies current to the capacitor responsive to receiving either the first or second signal. The amplitude of the feedback voltage is thus equal to the absolute value of the peak differential amplitude of the input signal.

Abstract: A peak voltage detector is used to detect the absolute value of the peak differential amplitude of a differential input signal. The peak voltage detector includes a differential amplifier receiving the differential input signal and generating a corresponding pair of differential output signals. The voltage detector also includes a capacitor on which an output signal is generated. A first differential comparator generates a first signal whenever the differential voltage from the differential amplifier is greater than the voltage of the output signal. A second differential comparator generates a second signal whenever the negative of the differential voltage from the differential amplifier is greater than the voltage of the output signal. A current source applies current to the capacitor responsive to receiving either the first or second signal. The amplitude of the feedback voltage is thus equal to the absolute value of the peak differential amplitude of the input signal.

Abstract: A signal amplitude threshold detector includes a comparator having first and second inputs. An input signal is coupled to the first input of the comparator. The second input of the comparator receives a reference voltage from a reference voltage generator. The signal amplitude threshold detector also includes a parallel combination of a capacitor and a resistor coupled between the first input of the comparator and ground. The comparator generates a first logic level when the amplitude of the input signal is less than the amplitude of the reference voltage, and it generates a second logic level when the amplitude of the input signal is greater than the amplitude of the reference voltage. The input signal may be supplied by a peak voltage detector, which supplies current to the capacitor when the peak amplitude of a signal is greater than the voltage on the capacitor.

Abstract: A variable gain amplifier is provided by including a gain control transistor with a differential amplifier. The differential amplifier has a first and second transistor each coupled to data inputs, which can receive a differential data signal. The gain control transistor is coupled between the drains of the first and second transistors. Control voltages are used to shunt differential current through the gain control transistor, providing variable gain with the maximum gain occurring when the control signals turn the gain control transistor off. A constant bias current is maintained by a pair of cascode transistors in parallel coupled to the sources of the first and second transistor.

Abstract: A data storage latch which permits forming a feedback loop for storage and permits storing data signals in an open loop configuration using logic circuit elements based on cross-coupled transistor loads.

Abstract: A monolithic integrated circuit memory control operating through the use of MOS field-effect transistors with diode or bipolar circuit arrangement for the bit line column switching.

Abstract: A fuse status detection circuit for determining the conduction of fuses used in integrated circuits is disclosed based on a flip-flop circuit containing the fuses which is set to an initial state during operation.

Abstract: A cross-coupled load logic gate family which will keep voltage at a logic gate output below that of a switching threshold and a subsequent logic gate during a charge disturbance upset.

Abstract: A memory system having voltage level circuit switching portions operated between signal lines stabilized by additional capacitance.

Abstract: An interface circuit to couple logic signals from a logic gate of one kind of logic family to a logic gate of another operating at different logic state voltages, where a latch circuit is used with the first of two cascaded inverters to provide the desired interface circuit signal characteristics. One inverter is provided with a supply reduction threshold means as is another inverter in the latch so that the two inverters perform substantially similarly to one another. The latch allows independent adjustments of opposite direction logic level transitions to provide a desired noise margin.