Patents by Inventor Robert Lowell Kanzelman
Robert Lowell Kanzelman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11922130Abstract: In an approach for optimization of integer arithmetic expressions implemented as a Boolean logic circuit, a processor converts arithmetic operators in an arithmetic expression into adders. A processor identifies a topological order of the adders. A processor merges the adders based on the topological order into a multi-operand adder. A processor converts the multi-operand adder to a compressor tree and a two-operand adder. A processor performs the arithmetic expression based on the converted multi-operand adder.Type: GrantFiled: December 10, 2021Date of Patent: March 5, 2024Assignee: International Business Machines CorporationInventors: Mihir Choudhury, Ayesha Akhter, Alexander Ivrii, Robert Lowell Kanzelman
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Publication number: 20230394212Abstract: An example system includes a processor to receive a high-level design representation of a system architecture. The processor can synthesize a logic design and generate an associated synthesis history based on the high-level hardware design representation. The processor can then execute an equivalence check between the high-level design and the synthesized logic design based on the generated synthesis history.Type: ApplicationFiled: June 1, 2022Publication date: December 7, 2023Inventors: Alexander IVRII, Jason Raymond BAUMGARTNER, Robert Lowell KANZELMAN, Mark Allen WILLIAMS, Mihir CHOUDHURY, Ayesha AKHTER
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Publication number: 20230185528Abstract: In an approach for optimization of integer arithmetic expressions implemented as a Boolean logic circuit, a processor converts arithmetic operators in an arithmetic expression into adders. A processor identifies a topological order of the adders. A processor merges the adders based on the topological order into a multi-operand adder. A processor converts the multi-operand adder to a compressor tree and a two-operand adder. A processor performs the arithmetic expression based on the converted multi-operand adder.Type: ApplicationFiled: December 10, 2021Publication date: June 15, 2023Inventors: MIHIR CHOUDHURY, Ayesha Akhter, ALEXANDER IVRII, Robert Lowell Kanzelman
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Publication number: 20230072735Abstract: A processor receives an expression of design refinement intent with regard to an entity forming a part of a modular circuit design. The entity is defined by a hardware description language (HDL) file, and the expression of design refinement intent identifies an intent region within an implementation of the entity and specifies replacement logic for the region. Based on the expression of design refinement intent, the processor automatically modifies the HDL file by replacing logic within the intent region with the replacement logic. The processor then performs logical synthesis to generate a gate list representation of the modular circuit design as modified.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Ali S. El-Zein, Wolfgang Roesner, Stephen Gerard Shuma, Robert Lowell Kanzelman, Michael Hemsley Wood, Chung-Lung K. Shum, Gabor Bobok, Robert James Shadowen, Viresh Paruthi, Derek E. Williams
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Patent number: 7996800Abstract: System and software for verifying that a model of an integrated circuit satisfies its specification includes performing a sequence of at least one sequential transformation on a sequential model of the integrated circuit to produce a simplified sequential model of the integrated circuit. Thereafter, the simplified sequential model is unfolded for N time steps to create a combinational representation of the design. A sequence of at least one combinational transformation algorithms is then performed on the unfolded design to produce a simplified unfolded model. Finally, an exhaustive search algorithm is performed on the simplified unfolded model. The sequence of sequential transformations may include a sequential redundancy removal (SRR) algorithm and/or another sequential algorithm such as a retiming transformation. The combinational transformations may include a combinational redundancy removal algorithm or a logic re-encoding algorithm.Type: GrantFiled: March 26, 2008Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgarter, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Patent number: 7930672Abstract: A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool then reduces the design to create a reduced design using the one or more techniques and attempts to generate a valid solution for the property on the reduced design. The logic verification tool determines whether a valid solution is generated, and, if not, replaces the design with the reduced design. Until a valid solution is generated, the logic verification tool iteratively performs the selecting, reducing, determining and replacing steps.Type: GrantFiled: February 6, 2008Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Patent number: 7921394Abstract: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is generated. A recursive extraction of one or more next states of selected registers is generated using the binary decision diagram analysis of the first target set and the primary input set. The recursive extraction is decomposed to generate a second target set, and the second target set is verified.Type: GrantFiled: December 7, 2007Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Patent number: 7913218Abstract: A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.Type: GrantFiled: December 12, 2007Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Patent number: 7908575Abstract: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is generated. A recursive extraction of one or more next states of selected registers is generated using the binary decision diagram analysis of the first target set and the primary input set. The recursive extraction is decomposed to generate a second target set, and the second target set is verified.Type: GrantFiled: August 31, 2007Date of Patent: March 15, 2011Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Patent number: 7882459Abstract: A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from a set of applicable simplification modes is selected, wherein said simplification mode is an AND/OR simplification mode, and a simplification of the initial design according to the first simplification mode is performed to generate a reduced design. Whether a size of the reduced design is less than a size of the initial design is determined and, in response to determining that the size of the reduced design is less than the size of the initial design, the initial design is replaced with the reduced design.Type: GrantFiled: November 26, 2007Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Patent number: 7831937Abstract: A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.Type: GrantFiled: December 12, 2007Date of Patent: November 9, 2010Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Patent number: 7823093Abstract: A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from a set of applicable simplification modes is selected, wherein said simplification mode is an AND/OR simplification mode, and a simplification of the initial design according to the first simplification mode is performed to generate a reduced design. Whether a size of the reduced design is less than a size of the initial design is determined and, in response to determining that the size of the reduced design is less than the size of the initial design, the initial design is replaced with the reduced design.Type: GrantFiled: November 26, 2007Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Patent number: 7779378Abstract: An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint net where the modified constraint net is FALSE for all cycles after any cycle in which the original constraint is FALSE. The method may include, instead of eliminating constraints, determining that the verification result is a target-not-asserted result and that the second netlist constraints are a superset of the first netlist constraints or that the verification result is a target-asserted result and that the first netlist constraints are a superset of the second netlist constraints. In either case, the method may include creating the composite netlist by importing all of the original constraints into the composite netlist.Type: GrantFiled: July 26, 2008Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Patent number: 7509605Abstract: An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint net where the modified constraint net is FALSE for all cycles after any cycle in which the original constraint is FALSE. The method may include, instead of eliminating constraints, determining that the verification result is a target-not-asserted result and that the second netlist constraints are a superset of the first netlist constraints or that the verification result is a target-asserted result and that the first netlist constraints are a superset of the second netlist constraints. In either case, the method may include creating the composite netlist by importing all of the original constraints into the composite netlist.Type: GrantFiled: December 12, 2005Date of Patent: March 24, 2009Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Publication number: 20090049416Abstract: An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint net where the modified constraint net is FALSE for all cycles after any cycle in which the original constraint is FALSE. The method may include, instead of eliminating constraints, determining that the verification result is a target-not-asserted result and that the second netlist constraints are a superset of the first netlist constraints or that the verification result is a target-asserted result and that the first netlist constraints are a superset of the second netlist constraints. In either case, the method may include creating the composite netlist by importing all of the original constraints into the composite netlist.Type: ApplicationFiled: July 26, 2008Publication date: February 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Publication number: 20080178132Abstract: System and software for verifying that a model of an integrated circuit satisfies its specification includes performing a sequence of at least one sequential transformation on a sequential model of the integrated circuit to produce a simplified sequential model of the integrated circuit. Thereafter, the simplified sequential model is unfolded for N time steps to create a combinational representation of the design. A sequence of at least one combinational transformation algorithms is then performed on the unfolded design to produce a simplified unfolded model. Finally, an exhaustive search algorithm is performed on the simplified unfolded model. The sequence of sequential transformations may include a sequential redundancy removal (SRR) algorithm and/or another sequential algorithm such as a retiming transformation. The combinational transformations may include a combinational redundancy removal algorithm or a logic re-encoding algorithm.Type: ApplicationFiled: March 26, 2008Publication date: July 24, 2008Inventors: Jason Raymond Baumgarter, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Publication number: 20080127002Abstract: A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool then reduces the design to create a reduced design using the one or more techniques and attempts to generate a valid solution for the property on the reduced design. The logic verification tool determines whether a valid solution is generated, and, if not, replaces the design with the reduced design. Until a valid solution is generated, the logic verification tool iteratively performs the selecting, reducing, determining and replacing steps.Type: ApplicationFiled: February 6, 2008Publication date: May 29, 2008Inventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Patent number: 7380221Abstract: A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from a set of applicable simplification modes is selected, wherein said simplification mode is an AND/OR simplification mode, and a simplification of the initial design according to the first simplification mode is performed to generate a reduced design. Whether a size of the reduced design is less than a size of the initial design is determined and, in response to determining that the size of the reduced design is less than the size of the initial design, the initial design is replaced with the reduced design.Type: GrantFiled: March 22, 2005Date of Patent: May 27, 2008Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Patent number: 7370292Abstract: A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool then reduces the design to create a reduced design using the one or more techniques and attempts to generate a valid solution for the property on the reduced design. The logic verification tool determines whether a valid solution is generated, and, if not, replaces the design with the reduced design. Until a valid solution is generated, the logic verification tool iteratively performs the selecting, reducing, determining and replacing steps.Type: GrantFiled: December 14, 2004Date of Patent: May 6, 2008Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi
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Patent number: 7360185Abstract: System and software for verifying that a model of an integrated circuit satisfies its specification includes performing a sequence of at least one sequential transformation on a sequential model of the integrated circuit to produce a simplified sequential model of the integrated circuit. Thereafter, the simplified sequential model is unfolded for N time steps to create a combinational representation of the design. A sequence of at least one combinational transformation algorithms is then performed on the unfolded design to produce a simplified unfolded model. Finally, an exhaustive search algorithm is performed on the simplified unfolded model. The sequence of sequential transformations may include a sequential redundancy removal (SRR) algorithm and/or another sequential algorithm such as a retiming transformation. The combinational transformations may include a combinational redundancy removal algorithm or a logic re-encoding algorithm.Type: GrantFiled: February 3, 2005Date of Patent: April 15, 2008Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgarter, Robert Lowell Kanzelman, Hari Mony, Viresh Paruthi