Patents by Inventor Robert M. Averill
Robert M. Averill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10248749Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: GrantFiled: February 15, 2018Date of Patent: April 2, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Patent number: 10223487Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: GrantFiled: February 13, 2017Date of Patent: March 5, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Publication number: 20180173817Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: ApplicationFiled: February 15, 2018Publication date: June 21, 2018Inventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Patent number: 9977851Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: GrantFiled: November 16, 2017Date of Patent: May 22, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Publication number: 20180075171Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: ApplicationFiled: November 16, 2017Publication date: March 15, 2018Inventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Publication number: 20180046734Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: ApplicationFiled: February 13, 2017Publication date: February 15, 2018Inventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Publication number: 20180046741Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: ApplicationFiled: August 11, 2016Publication date: February 15, 2018Inventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Patent number: 9892222Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.Type: GrantFiled: August 11, 2016Date of Patent: February 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert M. Averill, III, Erwin Behnen, David S. Wolpert
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Patent number: 9092591Abstract: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.Type: GrantFiled: April 10, 2014Date of Patent: July 28, 2015Assignee: International Business Machines CorporationInventors: Charles J. Alpert, Robert M. Averill, III, Eric J. Fluhr, Zhuo Li, Tuhin Mahmud, Jose L. P. Neves, Stephen T. Quay, Chin Ngai Sze, Yaoguang Wei
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Patent number: 9038009Abstract: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.Type: GrantFiled: December 9, 2013Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Charles Jay Alpert, Robert M. Averill, III, Zhuo Li, Jose L. P. Neves, Stephen T. Quay
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Publication number: 20140223397Abstract: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.Type: ApplicationFiled: April 10, 2014Publication date: August 7, 2014Applicant: International Business Machines CorporationInventors: Charles J. Alpert, Robert M. Averill, III, Eric J. Fluhr, Zhuo Li, Tuhin Mahmud, Jose L.P. Neves, Stephen T. Quay, Chin Ngai Sze, Yaoguang Wei
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Publication number: 20140195998Abstract: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.Type: ApplicationFiled: January 9, 2013Publication date: July 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles J. Alpert, Robert M. Averill, III, Eric J. Fluhr, Zhuo Li, Tuhin Mahmud, Jose L.P. Neves, Stephen T. Quay, Chin Ngai Sze, Yaoguang Wei
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Patent number: 8769468Abstract: Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design.Type: GrantFiled: January 9, 2013Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Charles J. Alpert, Robert M. Averill, III, Eric J. Fluhr, Zhuo Li, Tuhin Mahmud, Jose L. P. Neves, Stephen T. Quay, Chin Ngai Sze, Yaoguang Wei
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Publication number: 20140101629Abstract: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.Type: ApplicationFiled: December 9, 2013Publication date: April 10, 2014Applicant: International Business Machines CorporationInventors: Charles Jay Alpert, Robert M. Averill, III, Zhuo Li, Jose L. P. Neves, Stephen T. Quay
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Patent number: 8640075Abstract: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.Type: GrantFiled: June 1, 2012Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Charles Jay Alpert, Robert M. Averill, III, Zhuo Li, Jose L. P. Neves, Stephen T. Quay
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Publication number: 20130326450Abstract: Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.Type: ApplicationFiled: June 1, 2012Publication date: December 5, 2013Applicant: International Business Machines CorporationInventors: Charles Jay Alpert, Robert M. Averill, Zhuo Li, Jose L. P. Neves, Stephen T. Quay
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Patent number: 7568176Abstract: A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more interconnecting elements and designating at least one child to receive a pushdown of the one or more interconnecting elements from the parent level. For each child designated to receive the pushdown of the one or more interconnecting elements, the method further includes determining a physical coverage area of the child, identifying which of the one or more interconnecting elements within the physical coverage area of the child to pushdown into the child, generating an interconnecting element pushdown list for the child, including wiring layer information, and outputting the interconnecting element pushdown list.Type: GrantFiled: June 4, 2007Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: Adam R. Jatkowski, Robert M. Averill, III, Joseph J. Palumbo
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Publication number: 20080301607Abstract: A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more interconnecting elements and designating at least one child to receive a pushdown of the one or more interconnecting elements from the parent level. For each child designated to receive the pushdown of the one or more interconnecting elements, the method further includes determining a physical coverage area of the child, identifying which of the one or more interconnecting elements within the physical coverage area of the child to pushdown into the child, generating an interconnecting element pushdown list for the child, including wiring layer information, and outputting the interconnecting element pushdown list.Type: ApplicationFiled: June 4, 2007Publication date: December 4, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Adam R. Jatkowski, Robert M. Averill, III, Joseph J. Palumbo
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Patent number: 5304927Abstract: Monitoring a series of products of the kind in which the presence of foreign bodies in the product being monitored is detected by the characteristic magnetic field phase difference each material exhibits. The signal generated by a satisfactory product having no foreign body in it is used as the datum for judging whether the next subsequent product is free from a foreign body or not.Type: GrantFiled: February 4, 1991Date of Patent: April 19, 1994Assignee: Cintex LimitedInventors: Neil E. Thomas, Clive F. Kittel, Robert M. Averill, Christopher Marcus, Ian W. D. Cox