Abstract: There are provided herein, inter alia, complexes, compositions and methods for a vaccine for COVID-19. The cell-penetrating complexes provided herein may include a nucleic acid non-covalently bound to a cationic amphipathic polymer, the cationic amphipathic polymer including a pH-sensitive immolation domain. The cell-penetrating complexes provided herein are, inter alia, useful in vaccines, wherein the vaccine includes a ribonucleic acid including a sequence encoding a viral protein, a nucleic acid adjuvant and a cationic amphipathic polymer provided herein including embodiments thereof.

Abstract: There are provided herein, inter alia, cationic amphipathic polymers, complexes, and compositions comprising same, and methods for their use including for the delivery of therapeutic, diagnostic and imaging agents, including nucleic acids, into a cell. The complexes, compositions and methods may facilitate delivery and targeted release of the therapeutic, diagnostic and imaging agents to particular cell types and tissues.

Abstract: In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

Abstract: In a memory system, which includes a dynamic random access memory (DRAM) that has to be precharged before the contents thereof can be selectively read out into a static register, there is provided means for reading the memory contents of the memory cells of a part or the whole of a row of memory cells of the DRAM into the static register while concurrently precharging the DRAM for a subsequent read-out command. This reduces the overall cycle time of the memory array since read-out of the static register can occur during precharge.

Abstract: In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing a mechanism for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

Abstract: In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, clip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.