Patents by Inventor Robert M. English
Robert M. English has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7194595Abstract: A technique translates a hybrid virtual volume (vvol) having a file system that contains intermingled virtual and physical volume block numbers (vbns) into a “pure” stream of virtual vbns (vvbns). The stream of vvbns is illustratively embodied as an output file system data stream of a vvol image that is transferred by a source storage system (“source”) to a destination storage system (“destination”) in accordance with image transfer operations, such as volume copying and synchronous or asynchronous mirroring, provided by a volume replication facility. The blocks that are sent as part of the image transfer are selected from a container file of the hybrid vvol on the source. In particular, the invention is directed to a technique for translating physical vbns (pvbns) of a source aggregate on the source to pure vvbns of the output file system data stream that can be used on a destination aggregate of the destination, where embedded pvbns in the source hybrid vvol image are not valid.Type: GrantFiled: September 27, 2004Date of Patent: March 20, 2007Assignee: Network Appliance, Inc.Inventors: Robert L. Fair, Ashish Prakash, Eric Hamilton, John K. Edwards, Robert M. English
-
Patent number: 7185144Abstract: A semi-static distribution technique distributes parity across disks of an array. According to the technique, parity is distributed (assigned) across the disks of the array in a manner that maintains a fixed pattern of parity blocks among the stripes of the disks. When one or more disks are added to the array, the semi-static technique redistributes parity in a way that does not require recalculation of parity or moving of any data blocks. Notably, the parity information is not actually moved; the technique merely involves a change in the assignment (or reservation) for some of the parity blocks of each pre-existing disk to the newly added disk.Type: GrantFiled: November 24, 2003Date of Patent: February 27, 2007Assignee: Network Appliance, Inc.Inventors: Peter F. Corbett, Steven R. Kleiman, Robert M. English
-
Patent number: 7152069Abstract: A system and method enable a storage operating system to partition data into fixed sized data blocks that can be written to disk without having to copy the contents of memory buffers (mbufs). The storage operating system receives data from a network and stores the data in chains of mbufs having various lengths. However, the operating system implements a file system that manipulates data in fixed sized data blocks. Therefore, a set of buffer pointers is generated by the file system to define a fixed sized block of data stored in the mbufs. The set of buffer pointers address various portions of data stored in one or more mbufs, and the union of the data portions form a single fixed sized data block. A buffer header stores the set of pointers associated with a given data block, and the buffer header is passed among different layers in the storage operating system.Type: GrantFiled: October 15, 2002Date of Patent: December 19, 2006Assignee: Network Appliance, Inc.Inventors: Douglas J. Santry, Robert M. English
-
Patent number: 7139817Abstract: The invention provides for managing information for multiple devices. Each of a set of devices retrieves information from a sequence of servers. A device when starting up reads a list of file names, reads information from each file in sequence, and resolves conflicts among files to present a consistent configuration on each restart of each device. A file includes a sequence of <name, value> pairs. In those cases when two variables have the same name, an operator associated with the second pair indicates whether to overwrite the first value or to edit the first value, such as by appending the second value. One of the pairs indicates the list of file names itself. When the list of file names is changed, the device for which the change is made re-reads the sequence of files and repeats its determination of the pairs, until the list of file names is stabilized.Type: GrantFiled: June 12, 2001Date of Patent: November 21, 2006Assignee: Network Appliance, Inc.Inventors: Robert M. English, Szu-Wen Kuo, Brian Quirion
-
Patent number: 7080278Abstract: A technique efficiently corrects multiple storage device failures in a storage array. The storage array comprises a plurality of concatenated sub-arrays, wherein each sub-array includes a set of data storage devices and a local parity storage device that stores values used to correct a failure of a single device within a row of blocks, e.g., a row parity set, in the sub-array. Each sub-array is assigned diagonal parity sets identically, as if it were the only one present using a double failure protection encoding method. The array further includes a single, global parity storage device holding diagonal parity computed by logically adding together equivalent diagonal parity sets in each of the sub-arrays.Type: GrantFiled: March 8, 2002Date of Patent: July 18, 2006Assignee: Network Appliance, Inc.Inventors: Steven R. Kleiman, Robert M. English, Peter F. Corbett
-
Patent number: 7073115Abstract: A technique efficiently corrects multiple storage device failures in a storage array using a combination of a single diagonal parity group and multiple row parity groups. The storage array includes a plurality of concatenated sub-arrays, wherein each sub-array includes a set of data storage devices and a parity storage device. Each row parity group is associated with a sub-array of the array. The array further includes a global parity storage device holding diagonal parity computed across the concatenation of the sub-arrays. Instead of requiring that each parity group contain both a row parity device and a diagonal parity device, the array is composed of a collection of row parity groups. Diagonal parity is calculated across the full array.Type: GrantFiled: December 28, 2001Date of Patent: July 4, 2006Assignee: Network Appliance, Inc.Inventors: Robert M. English, Peter F. Corbett, Steven R. Kleiman
-
Patent number: 6993701Abstract: A “row-diagonal” (R-D) parity technique reduces overhead of computing diagonal parity for a storage array adapted to enable efficient recovery from the concurrent failure of two storage devices in the array. The diagonal parity is computed along diagonal parity sets that collectively span all data disks and a row parity disk of the array. The parity for all of the diagonal parity sets except one is stored on the diagonal parity disk. The R-D parity technique provides a uniform stripe depth and an optimal amount of parity information.Type: GrantFiled: December 28, 2001Date of Patent: January 31, 2006Assignee: Network Appliance, Inc.Inventors: Peter F. Corbett, Steven R. Kleiman, Robert M. English
-
Patent number: 6874027Abstract: A method and system for providing the functionality of dynamically-allocated threads in a multithreaded system, in which the operating system provides only statically-allocated threads. With this functionality, a relatively large number of threads can be maintained without a relatively large amount of overhead (either in memory or processor time), and it remains possible to produce program code without undue complexity. A plurality of dynamically-allocated threads are simulated using a single statically-allocated thread, but with state information regarding each dynamically-allocated thread maintained within the single statically-allocated thread. The single statically-allocated thread includes, for each procedure call that would otherwise introduce a new simulated thread, a memory block including (1) a relatively small procedure call stack for the new simulated thread, and (2) a relatively small collection of local variables and other state information for the new simulated thread.Type: GrantFiled: June 9, 2000Date of Patent: March 29, 2005Assignee: Network Appliance, Inc.Inventor: Robert M. English
-
Patent number: 6766515Abstract: A system and a method of scheduling a plurality of threads from a multi-threaded program. A shared arena is provided in user memory, wherein the shared arena includes a register save area for each of the plurality of threads. A processor, when allocated to the application, executes the application's user-level scheduler and selects a user-level thread from a plurality of available threads, wherein the step of selecting includes the step of reading register context associated with the selected thread from one of the plurality of register save areas. In multikernel systems, kernels having access to an application's register save areas can execute preempted threads from that application with no kernel-to-kernel communication. Likewise, kernels having access to an application's user-level run queues can execute ready-to-run threads from that application with no kernel-to-kernel communication.Type: GrantFiled: February 18, 1997Date of Patent: July 20, 2004Assignee: Silicon Graphics, Inc.Inventors: Nawaf K. Bitar, Robert M. English, Rajagopal Ananthanarayanan
-
Patent number: 6714960Abstract: A precise earnings-based time-share scheduler schedules multiple jobs in a computer system by apportioning earnings, at scheduler ticks. Earnings are apportioned to jobs based on actual time a job spent in a queue requesting execution on a central processing unit (CPU) in the computer system between scheduler ticks and amounts of time jobs ran on the CPU between scheduler ticks. At the end of a time slice, a job is selected for execution on the processor based on earnings apportioned to each job.Type: GrantFiled: November 20, 1996Date of Patent: March 30, 2004Assignee: Silicon Graphics, Inc.Inventors: Nawaf K. Bitar, Robert M. English, Rajagopal Ananthanarayanan
-
Publication number: 20030126523Abstract: A “row-diagonal” (R-D) parity technique reduces overhead of computing diagonal parity for a storage array adapted to enable efficient recovery from the concurrent failure of two storage devices in the array. The diagonal parity is computed along diagonal parity sets that collectively span all data disks and a row parity disk of the array. The parity for all of the diagonal parity sets except one is stored on the diagonal parity disk. The R-D parity technique provides a uniform stripe depth and an optimal amount of parity information.Type: ApplicationFiled: December 28, 2001Publication date: July 3, 2003Inventors: Peter F. Corbett, Steven R. Kleiman, Robert M. English
-
Publication number: 20030126522Abstract: A technique efficiently corrects multiple storage device failures in a storage array using a combination of a single diagonal parity group and multiple row parity groups. The storage array comprises a plurality of concatenated sub-arrays, wherein each sub-array includes a set of data storage devices and a parity storage device. Each row parity group is associated with a sub-array of the array. The array further includes a global parity storage device holding diagonal parity computed across the concatenation of the sub-arrays. Instead of requiring that each parity group contain both a row parity device and a diagonal parity device, the array is composed of a collection of row parity groups. Diagonal parity is calculated across the full array.Type: ApplicationFiled: December 28, 2001Publication date: July 3, 2003Inventors: Robert M. English, Peter F. Corbett, Steven R. Kleiman
-
Patent number: 6418460Abstract: A system and method for inexpensively detecting preempted execution entities such as threads without kernel involvement. In a computer system having a memory and one or more processors, a shared memory arena is formed in user space within the memory. A preempt bit vector is then formed within the shared memory arena such that the preempt bit vector is accessible to any of a plurality of execution entities running in user mode. The preempt bit vector includes a plurality of rbits, wherein each rbit is associated with one of the plurality of execution entities and wherein an rbit is marked whenever its associated execution entity is preempted. Detection of preempted threads then becomes a matter of reading, via program code executing in user mode on one of the plurality of processors, bits in the preempt bit vector to detect preempted execution entities.Type: GrantFiled: February 18, 1997Date of Patent: July 9, 2002Assignee: Silicon Graphics, Inc.Inventors: Nawaf K. Bitar, Robert M. English, Rajagopal Ananthanarayanan
-
Patent number: 6353844Abstract: A batch job scheduler facility schedules batch jobs in a general purpose multiprocessor system having resources, such as processors and memory, and running interactive and batch jobs. The resources are allocated to the batch jobs. Completion times are calculated and guaranteed for the batch jobs based on the resources allocated to the batch jobs. The completion times are calculated and guaranteed without static partitioning, resulting in improved utilization of system resources. Batch-critical batch jobs are defined which require all their allocated resources to complete by their guaranteed completion time. The batch jobs are scheduled so that batch jobs and interactive jobs compete for the same resources. Batch-critical jobs are permitted to obtain all their allocated resources.Type: GrantFiled: December 23, 1996Date of Patent: March 5, 2002Assignee: Silicon Graphics, Inc.Inventors: Nawaf K. Bitar, Robert M. English
-
Patent number: 5928322Abstract: A low-latency real-time dispatching scheme performed by the operating system of a general purpose multiprocessor system having N processors, assigns a priority to each of multiple real-time threads to be executed on the N processors. The multiple real-time threads include up to N top priority real-time threads, which are bound to a corresponding processor. The assigned priority of each bound real-time thread is the highest priority for being executed on its corresponding processor, and any other real-time thread being executed on the corresponding processor is preempted if the bound real-time thread becomes runnable.Type: GrantFiled: November 20, 1996Date of Patent: July 27, 1999Assignee: Silicon Graphics, Inc.Inventors: Nawaf K. Bitar, Rajagopal Ananthanarayanan, Robert M. English
-
Patent number: 5872963Abstract: A system and method for context switching between a first and a second execution entity (such as a thread) without having to enter into protected kernel mode. The system includes a memory and a plurality of processors, wherein each of the plurality of processors operates within both a user mode and a protected kernel mode and includes a program counter and a plurality N of registers. The first and second execution entities have user states defined by a program counter value, a context identifier value and N register values. To switch context, an execution entity such as a thread, while in user mode, writes the user state of the first execution entity to memory. It then restores the user state of the second execution entity by writing register values associated with the second execution entity to all but a first register and writing the context identifier value to a context identifier location.Type: GrantFiled: February 18, 1997Date of Patent: February 16, 1999Assignee: Silicon Graphics, Inc.Inventors: Nawaf K. Bitar, Robert M. English, Rajagopal Ananthanarayanan, Alexander D. Petruncola, David Craig
-
Patent number: 5564031Abstract: In a digital computer, a circular queue of registers in a register file are allocated as temporary local storage for procedures rather than using the known caller/callee save convention in order to minimize main memory references. A called procedure dynamically allocates local registers as needed without regard to registers used by the caller of the procedure or by any callee of the procedure, whereby register allocation is not restricted by any predetermined window size. Local registers, including parameter passing registers, are allocated in the called procedure, rather than a priori at compile time, by adjusting register stack pointer values. Only the number of registers actually required by the procedure need by allocated. Optionally, rotating registers may be allocated among the local registers. Stack pointer values are stored in one of the parameter passing registers when a procedure is called.Type: GrantFiled: April 12, 1996Date of Patent: October 8, 1996Assignees: Hewlett-Packard Company, Hitachi, Ltd.Inventors: Frederic C. Amerson, Robert M. English, Rajiv Gupta, Tan Watanabe
-
Patent number: 5481694Abstract: An electronic data storage system including a memory, a plurality of magnetic disk units, and a controller. The memory contains an index cross-referencing logical address with physical addresses, an obsolete list and a free list. In response to a "write " command, the controller selects a physical address according to which segment can be used the most quickly, appends a tag to the data to be written, and writes the data to the selected segment. Appropriate entries are made in the index and the free list. The system recovers from memory loss by using a checkpoint log and a set of checkpoint segments on the disk that together contain backups of the index and other critical information needed to restore the system. Group indices are used for roll-back groups; operations on data in a group are invisible outside the group until after a "commit " command is issued.Type: GrantFiled: April 24, 1992Date of Patent: January 2, 1996Assignee: Hewlett-Packard CompanyInventors: Chia-Chiang Chao, Robert M. English, David M. Jacobson, Alexander A. Stepanov, Andrew J. Wilkes
-
Patent number: 5345575Abstract: An indirectly accessed disk storage device comprises a rotating disk memory coupled to an intelligent disk controller. The intelligent disk controller responds to a request to store a packet of data by determining which storage location of the rotating disk memory are available and by selecting from among the available locations a location that can be accessed in a minimum amount of time relative to access time of any other available location. The intelligent disk controller makes its selection dynamically by monitoring the current position of the recording head of the rotating disk memory and by searching a record of available locations to select an optimal location. The intelligent disk controller then stores the packet of data on the rotating disk memory. By optimizing such data write operations, the indirectly accessed disk storage device also effectively optimizes data read operations.Type: GrantFiled: September 26, 1991Date of Patent: September 6, 1994Assignee: Hewlett-Packard CompanyInventors: Robert M. English, Alexander A. Stepanov