Abstract: Methods and systems for load balancing a plurality of entities, such as firewalls, in a network environment are disclosed. In particular, the load balancing of firewalls on a bidirectional traffic path is performed using a single device that controls both incoming and outgoing traffic through the firewalls. The single device may include virtual routers for controlling the bidirectional traffic through the firewalls. A first virtual router may control incoming traffic to the firewalls and the other virtual router may control outgoing traffic to the firewalls. The virtual routers are logical partitions of the device layered on the physical resources of the device. The virtual routers share all or portions of the physical resources of the single device.

Abstract: A processor for use in a digital data processing system includes a data path which is controlled by microinstructions from the processor's control circuits. The data path includes a plurality of registers and an arithmetic and logic unit. The source data processed by the arithmetic and logic unit is obtained from the registers and elsewhere in the system as identified by selected fields of the microinstruction, and the processed data is stored in destinations also identified by the source selection fields or other locations. The destination selection field of the microinstruction selects a source identification or another destination as the selected destination.

Abstract: It is desirable to bypass the defects within a cache memory so that a high percentage of the cache is usable; otherwise the entire chip containing the cache memory must be scrapped. Since VLSI chips with a small number of defects form a large proportion of the scrapped yield, rendering chips with a small number of defects usable greatly increases the production yield and reduces the cost of each chip. Therefore, a cache memory is provided wherein each memory location includes a bit which is set in response to a detected hardware defect. Preferably, each memory location in the cache is tested by error detecting software, which sets the defect bit in any memory location containing a defect. The defect bit is tested every time data is retrieved from each memory location, and a set defect bit prohibits further use of a defective memory location.

Abstract: A processor for use in a digital data processing system including a main memory and a write buffer for buffering write data and associated addresses from the processor for storage in the storage locations identified by the associated addresses in the main memory. In response to selection occurances, such as a context switch, which cannot be detected outside of the processor, the processor asserts a signal which enables the write buffer to transfer all of its contents to the main memory. The write buffer, in turn, disables the processor while it is transferring data to the main memory.