Patents by Inventor Robert Maher

Robert Maher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240099872
    Abstract: A brace is provided including an upper support arm, a lower support arm, a hinge assembly configured to rotatably couple the upper support arm to the lower support arm, a plurality of cuffs, each coupled directly or indirectly to the upper support arm or the lower support arm and configured to receive a respective strap for securing the brace to an appendage of the subject, and a plurality of buckles, each configured to be coupled to a respective one of the plurality of cuffs and to receive one of the respective straps.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 28, 2024
    Inventors: Robert Bejarano, Edward Maher
  • Patent number: 11539585
    Abstract: Methods for, and network elements in, packet or optical transport networks are disclosed, including a network element comprising non-transitory computer readable medium storing computer-executable instructions configured as one or more software agents that when executed with computer hardware: determine a state of the network element, comprising comparing a current state of transient properties of the network element against a predetermined, expected state of the transient properties of the network element; and verify a state of other network elements or paths in the transport network by comparing a current state of one or more network-level constraints of the other network elements or paths against a predetermined, expected state of the one or more network-level constraints on the other network elements or paths. The computer hardware may further positively or negatively acknowledge received instructions to apply a configuration to the network element based on the determination and/or verification.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: December 27, 2022
    Assignee: Infineraa Corporation
    Inventors: Abhinava Shivakumar Sadasivarao, Loukas Paraschis, Sharfuddin Syed, Robert Maher
  • Publication number: 20220303014
    Abstract: A transceiver is herein described. The transceiver comprises an optical source providing an optical signal, a modulator receiving the optical signal and configured to encode data into the optical signal, a transmitter module to receive data to be encoded into the optical signal and having at least one drive circuit supplying driver signals to the modulator to cause the modulator to encode data into a carrier having a frequency band and a tone signal outside of the frequency band into the optical signal, a narrowband filter operable to receive a portion of the optical signal via an optical loopback, the optical signal having the encoded data and a first tone reflection of the tone signal at a first instant of time and to pass the first tone reflection, a polarimeter operable to receive the first tone reflection and determine a first tone polarization of the first tone reflection.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 22, 2022
    Inventors: Pierre Mertz, Han Hennry Sun, Robert Maher
  • Publication number: 20220029885
    Abstract: Methods for, and network elements in, packet or optical transport networks are disclosed, including a network element comprising non-transitory computer readable medium storing computer-executable instructions configured as one or more software agents that when executed with computer hardware: determine a state of the network element, comprising comparing a current state of transient properties of the network element against a predetermined, expected state of the transient properties of the network element; and verify a state of other network elements or paths in the transport network by comparing a current state of one or more network-level constraints of the other network elements or paths against a predetermined, expected state of the one or more network-level constraints on the other network elements or paths. The computer hardware may further positively or negatively acknowledge received instructions to apply a configuration to the network element based on the determination and/or verification.
    Type: Application
    Filed: July 22, 2021
    Publication date: January 27, 2022
    Inventors: Abhinava Shivakumar Sadasivarao, Loukas Paraschis, Sharfuddin Syed, Robert Maher
  • Patent number: 10373072
    Abstract: A method, system, and computer program product for performing cognitive-based dynamic tuning of a software-based system include monitoring live operation of the system, and determining whether tuning is needed based on the monitoring. Analyzing information and suggesting a change in one or more parameters is based on the determining, the information including an output of a learning algorithm that learns an effect of changes in one or more of the one or more parameters on performance of the system.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diane Britton, Reza Ghasemi, Chon N. Lei, Robert Maher, Vanessa V. Michelini
  • Publication number: 20170200091
    Abstract: A method, system, and computer program product for performing cognitive-based dynamic tuning of a software-based system include monitoring live operation of the system, and determining whether tuning is needed based on the monitoring. Analyzing information and suggesting a change in one or more parameters is based on the determining, the information including an output of a learning algorithm that learns an effect of changes in one or more of the one or more parameters on performance of the system.
    Type: Application
    Filed: January 8, 2016
    Publication date: July 13, 2017
    Inventors: Diane Britton, Reza Ghasemi, Chon N. Lei, Robert Maher, Vanessa V. Michelini
  • Publication number: 20150295794
    Abstract: In one embodiment, a computer-implemented method includes iteratively running a client application on two or more combinations of two or more hardware platforms and one or more software products, where the two or more hardware platforms and the one or more software products reside in an integrated evaluation appliance. The running of the client application on the two or more combinations is monitored by a computer processor. A result of running the client application on a first hardware platform and a result of running the client application on a second hardware platform are output, where the first hardware platform and the second hardware platform are among the two or more hardware platforms residing in the evaluation appliance.
    Type: Application
    Filed: September 30, 2014
    Publication date: October 15, 2015
    Inventors: Robert Maher, Elisabeth R. Stahl, Clarisse T. Taaffe-Hedglin
  • Publication number: 20150295793
    Abstract: In one embodiment, a computer-implemented method includes iteratively running a client application on two or more combinations of two or more hardware platforms and one or more software products, where the two or more hardware platforms and the one or more software products reside in an integrated evaluation appliance. The running of the client application on the two or more combinations is monitored by a computer processor. A result of running the client application on a first hardware platform and a result of running the client application on a second hardware platform are output, where the first hardware platform and the second hardware platform are among the two or more hardware platforms residing in the evaluation appliance.
    Type: Application
    Filed: April 10, 2014
    Publication date: October 15, 2015
    Applicant: International Business Machines Corporation
    Inventors: Robert Maher, Elisabeth R. Stahl, Clarisse T. Taaffe-Hedglin
  • Patent number: 9092395
    Abstract: A high availability/disaster recovery appliance test vehicle that contains a preconfigured high availability/disaster recovery solution for quick implementation at a test environment. The hardware and software components may be preconfigured with test applications and data and all the necessary networking, SAN and operating system requirements. This single shippable rack can be used to certify a multi site high availability/disaster recovery architecture that supports both local and site failover and site to site data replication. The unit is plug and play which reduces the effort required to begin the evaluation and reduces the number of IT teams that need to be involved. An apparatus and method for implementing the above high availability/disaster recovery vehicle are provided.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Andrew J. Bradfield, Paul Canevari, Kenneth W. Fleck, Robert Maher
  • Publication number: 20140181572
    Abstract: A high availability/disaster recovery appliance test vehicle that contains a preconfigured high availability/disaster recovery solution for quick implementation at a test environment. The hardware and software components may be preconfigured with test applications and data and all the necessary networking, SAN and operating system requirements. This single shippable rack can be used to certify a multi site high availability/disaster recovery architecture that supports both local and site failover and site to site data replication. The unit is plug and play which reduces the effort required to begin the evaluation and reduces the number of IT teams that need to be involved. An apparatus and method for implementing the above high availability/disaster recovery vehicle are provided.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew J. Bradfield, Paul Canevari, Kenneth W. Fleck, Robert Maher
  • Patent number: 8343716
    Abstract: A method of forming a variable pattern across a wafer using a reticle forms a plurality of first patterns on the wafer. The first pattern is repeated across the wafer and each first pattern has a first readable element. The method also forms a plurality of second patterns on the wafer. The second patterns is repeated across the wafer and each second pattern has a second readable element. The second patterns are positioned relative to the first patterns by aligning a first second pattern relative to one portion of a corresponding first pattern and then incrementally misaligning each successive second pattern in a row or a column relative to its corresponding first pattern. Thus, each corresponding first readable element and second readable element form a corresponding variable pattern.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: January 1, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Lee J. Jacobson, Francis J. McNally, Zualfquar Mohammed, Robert Maher
  • Patent number: 7900075
    Abstract: A pipelined computer system with power management control in accordance with one or both of a power management signal and a power management instruction.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: March 1, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin, Mark Bluhm
  • Patent number: 7900076
    Abstract: A power management method for a pipelined computer system in accordance with one or both of a power management signal and a power management instruction.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: March 1, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin, Mark Bluhm
  • Publication number: 20090098487
    Abstract: A method of forming a variable pattern across a wafer using a reticle forms a plurality of first patterns on the wafer. The first pattern is repeated across the wafer and each first pattern has a first readable element. The method also forms a plurality of second patterns on the wafer. The second patterns is repeated across the wafer and each second pattern has a second readable element. The second patterns are positioned relative to the first patterns by aligning a first second pattern relative to one portion of a corresponding first pattern and then incrementally misaligning each successive second pattern in a row or a column relative to its corresponding first pattern. Thus, each corresponding first readable element and second readable element form a corresponding variable pattern.
    Type: Application
    Filed: October 16, 2008
    Publication date: April 16, 2009
    Applicant: ANALOG DEVICES, INC.
    Inventors: Lee J. Jacobson, Francis J. McNally, Zualfquar Mohammed, Robert Maher
  • Patent number: 7509512
    Abstract: An instruction-initiated method for suspending operation of a pipelined data processor by selectively disabling a clock signal to pipeline subcircuitry in response to an instruction executed by the pipeline subcircuitry.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: March 24, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin, Mark Bluhm
  • Publication number: 20080109667
    Abstract: A power management method for a pipelined computer system in accordance with one or both of a power management signal and a power management instruction.
    Type: Application
    Filed: October 31, 2007
    Publication date: May 8, 2008
    Applicant: National Semiconductor Corporation
    Inventors: Robert Maher, Raul Garibay, Margaret Herubin, Mark Bluhm
  • Publication number: 20080098248
    Abstract: A pipelined computer system with power management control in accordance with one or both of a power management signal and a power management instruction.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 24, 2008
    Applicant: National Semiconductor Corporation
    Inventors: Robert Maher, Raul Garibay, Margaret Herubin, Mark Bluhm
  • Publication number: 20060227758
    Abstract: A method and apparatus is described that allow the creation of virtual routing domains in an IP network. These virtual routing domains allow individual networks to be configures so that it appears that its routing domain covers the entire IP address space. A network processing system is used to implement the virtual routing domains and to allow network traffic to cross the individual routing domains. The network processing system is able to use application layer information to allow the crossing of virtual routing domain boundaries. By examining application layer information the network processing system is able to look up customer/user information and use that information to determine destination virtual routing domains and route otherwise unroutable addresses between domains.
    Type: Application
    Filed: April 9, 2005
    Publication date: October 12, 2006
    Inventors: Ashwin Rana, Milton Lie, Robert Walls, Robert Maher
  • Patent number: 7120810
    Abstract: An instruction-initiated power management method for a pipelined data processor by which a clock signal to pipeline subcircuitry is selectively disabled in response to an instruction executed by the pipeline subcircuitry.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: October 10, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Robert Maher, Raul A. Garibay, Jr., Margaret R. Herubin, Mark Bluhm
  • Publication number: 20060200344
    Abstract: A method of reducing noise in an audio signal, comprising the steps of: using a furrow filter to select spectral components that are narrow in frequency but relatively broad in time; using a bar filter to select spectral components that are broad in frequency but relatively narrow in time; analyzing the relative energy distribution between the output of the furrow and bar filters to determine the optimal proportion of spectral components for the output signal; and reconstructing the audio signal to generate the output signal. A second pair of time-frequency filters may be used to further improve intelligibility of the output signal. The temporal relationship between the furrow filter output and the bar filter output may be monitored so that the fricative components are allowed primarily at boundaries between intervals with no voiced signal present and intervals with voice components. A noise reduction system for an audio signal.
    Type: Application
    Filed: March 7, 2005
    Publication date: September 7, 2006
    Inventors: Daniel Kosek, Robert Maher