Abstract: A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

Abstract: A dynamic random access memory (DRAM) circuit and its associated sub-word-line driver. The DRAM circuit includes a boost circuit, a main word line driver and a sub-word line driver. The boost circuit changes its output boost voltage, which lies between an internal supply voltage and an operating voltage, according to an input row access strobe (RAS) signal. The main word line driver is connected to the output terminal of the boost circuit and the main word line, selected according to input address decoding, is driven by the boost voltage. The sub-word line driver is connected to the main word line. An even or odd sub-word-line signal is generated according to the least significant bit of an input address so that voltage level on the main word line can be used to drive the corresponding sub-word line.