Patents by Inventor Robert May
Robert May has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230140389Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 30, 2022Publication date: May 4, 2023Applicant: Intel CorporationInventors: Aleksandar ALEKSOV, Adel A. ELSHERBINI, Kristof DARMAWIKARTA, Robert A. MAY, Sri Ranga Sai BOYAPATI
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Publication number: 20230101417Abstract: An isolator product includes a capacitor having a first plate formed in a first conductive integrated circuit layer and multiple second plates formed in a second conductive integrated circuit layer. Each second plate of the multiple second plates is separated from a next adjacent second plate by a gap in the second conductive integrated circuit layer. The multiple second plates are concentric.Type: ApplicationFiled: September 29, 2022Publication date: March 30, 2023Inventors: Michael Robert May, Fernando Naim Lavalle Aviles
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Patent number: 11583642Abstract: A refill assembly configured to be removably coupled to a reusable assembly of a medicinal inhaler is disclosed and includes a patient port, a canister actuable by the reusable assembly to deliver a dose of medicament to the patient port, and a sleeve which is selectively actuable by a user independently of the reusable assembly so as to act on the canister to deliver a dose of medicament. The refill assembly further includes an override element which engages the sleeve, the override element being moveable from a first position in which the sleeve is retained in a first position by the override element and a second position in which the sleeve is permitted to move to a second position upon depression of the sleeve by a user to cause a dose of medicament to be delivered to the patient port.Type: GrantFiled: April 25, 2018Date of Patent: February 21, 2023Assignee: Kindeva Drug Delivery L.P.Inventors: Robert May, David M. Molony, Iain G. McDerment
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Publication number: 20230038058Abstract: Systems, devices, and methods are discussed for providing ZTNA control across multiple related, but independently provisioned networks.Type: ApplicationFiled: August 9, 2021Publication date: February 9, 2023Applicant: Fortinet, Inc.Inventor: Robert A. May
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Patent number: 11574874Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.Type: GrantFiled: March 30, 2017Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Robert A. May, Sri Ranga Sai Boyapati, Kristof Darmawikarta, Hiroki Tanaka, Srinivas V. Pietambaram, Frank Truong, Praneeth Akkinepally, Andrew J. Brown, Lauren A. Link, Prithwish Chatterjee
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Publication number: 20230027030Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.Type: ApplicationFiled: September 30, 2022Publication date: January 26, 2023Inventors: Changhua LIU, Xiaoying GUO, Aleksandar ALEKSOV, Steve S. CHO, Leonel ARANA, Robert MAY, Gang DUAN
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Publication number: 20230015619Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).Type: ApplicationFiled: September 23, 2022Publication date: January 19, 2023Inventors: Kristof DARMAWAIKARTA, Robert MAY, Sashi KANDANUR, Sri Ranga Sai BOYAPATI, Srinivas PIETAMBARAM, Steve CHO, Jung Kyu HAN, Thomas HEATON, Ali LEHAF, Ravindranadh ELURI, Hiroki TANAKA, Aleksandar ALEKSOV, Dilan SENEVIRATNE
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Patent number: 11552010Abstract: The present disclosure is directed to systems and methods for providing a dielectric layer on a semiconductor substrate capable of supporting very high density interconnects (i.e., ?100 IO/mm). The dielectric layer includes a maleimide polymer in which a thiol-terminated functional group crosslinks with an epoxy resin. The resultant dielectric material provides a dielectric constant of less than 3 and a dissipation factor of less than 0.001. Additionally, the thiol functional group forms coordination complexes with noble metals present in the conductive structures, thus by controlling the stoichiometry of epoxy to polyimide, the thiol-polyimide may beneficially provide an adhesion enhancer between the dielectric and noble metal conductive structures.Type: GrantFiled: May 12, 2017Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: Robert A. May, Andrew J. Brown, Sri Ranga Sai Boyapati, Kristof Darmawikarta
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Publication number: 20220413233Abstract: An optical package comprising an optical die that is electrically coupled to a package substrate, and an optical interconnect adjacent the optical die. The optical interconnect comprises a first polarizing filter adjacent to a first lens, a second polarizing filter adjacent to a second lens; and a film comprising a magnetic material between the first polarizing filter and the second polarizing filter. The second polarizing filter is rotated with respect to the first polarizing filter and the magnetic material is to rotate a polarization vector of light incoming to the optical interconnect. An optical fiber interface port is immediately adjacent to the first lens. The second lens is immediately adjacent to an optical interface of the optical die.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Hiroki Tanaka, Kristof Darmawikarta, Brandon Marin, Robert May, Sri Ranga Sai Boyapati
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Publication number: 20220368719Abstract: Systems and methods for a security rating framework that translates compliance requirements to corresponding desired technical configurations to facilitate generation of security ratings for network elements is provided. According to one embodiment, a host network element executes a collection of security checks on at least a first network element. The execution is performed by receiving configuration data of the first network element pertaining to each security check of the collection of security checks in response to a request by the host network element and validating each security check by comparing the received configuration data pertaining to each security check with a pre-defined or configurable network security configuration recommendation to generate a compliance result. Further, the host network element generates a compliance report by aggregating the compliance results obtained by executing each security check of the collection of security checks.Type: ApplicationFiled: August 1, 2022Publication date: November 17, 2022Applicant: Fortinet, Inc.Inventors: Robert A. May, Tarlok Birdi
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Patent number: 11488918Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).Type: GrantFiled: October 31, 2018Date of Patent: November 1, 2022Assignee: Intel CorporationInventors: Kristof Darmawaikarta, Robert May, Sashi Kandanur, Sri Ranga Sai Boyapati, Srinivas Pietambaram, Steve Cho, Jung Kyu Han, Thomas Heaton, Ali Lehaf, Ravindranadh Eluri, Hiroki Tanaka, Aleksandar Aleksov, Dilan Seneviratne
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Publication number: 20220345491Abstract: Various approaches for providing scalable network access processing. In some cases, approaches discussed relate to systems and methods for providing scalable zero trust network access control.Type: ApplicationFiled: April 27, 2021Publication date: October 27, 2022Applicant: Fortinet, Inc.Inventors: Wenping Luo, Robert May, Kunal Marwah
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Patent number: 11477240Abstract: Systems and methods for remote monitoring of a Security Operations Center (SOC) via a mobile application are provided. According to one embodiment, a management service retrieves information regarding multiple network elements that are associated with an enterprise network and extracts parameters of the monitored network elements from the retrieved information. The management service prioritizes the monitored network elements by determining a severity level associated with security-related issues of the network elements and generates various monitoring views that summarize in real time various categories of potential security-related issues detected by the SOC. Further, the management service assigns a priority to each monitoring view and displays a video on the display device that cycles through monitoring views in accordance with their respective assigned priorities.Type: GrantFiled: June 26, 2019Date of Patent: October 18, 2022Assignee: Fortinet, Inc.Inventors: Robert A. May, Jordan E. Thompson
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Patent number: 11475790Abstract: Systems and methods are described for providing training to attendees of a network security training session through use of gamification. A virtual environment is created containing a network topology simulating a deployed network of network security devices for which teams of the attendees are to receive training. A 3D game interface is presented on a display of a computer system of an attendee. Based on a leaderboard server's game state, a problem-solving objective for the training session is presented on the display. The virtual environment facilitates interactions by the attendee with the network security devices via real web interfaces of corresponding full-feature virtual network security appliances in connection with attempts by the attendee to complete the objectives. Upon completion of an objective, the leaderboard server's game state is updated. Based on the game state of a group of objectives a second group of problem-solving objectives is presented to the attendee.Type: GrantFiled: June 28, 2019Date of Patent: October 18, 2022Assignee: Fortinet, Inc.Inventors: Robert A. May, Jordan E. Thompson, Jamie Pate
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Publication number: 20220319996Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: June 16, 2022Publication date: October 6, 2022Applicant: Intel CorporationInventors: Aleksandar Aleksov, Adel A. Elsherbini, Kristof Darmawikarta, Robert A. May, Sri Ranga Sai Boyapati
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Publication number: 20220285278Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.Type: ApplicationFiled: May 24, 2022Publication date: September 8, 2022Inventors: Jeremy D. ECTON, Hiroki TANAKA, Oscar OJEDA, Arnab ROY, Vahidreza PARICHEHREH, Leonel R. ARANA, Chung Kwang TAN, Robert A. MAY
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Patent number: 11425158Abstract: Systems and methods for a security rating framework that translates compliance requirements to corresponding desired technical configurations to facilitate generation of security ratings for network elements is provided. According to one embodiment, a host network element executes a collection of security checks on at least a first network element. The execution is performed by receiving configuration data of the first network element pertaining to each security check of the collection of security checks in response to a request by the host network element and validating each security check by comparing the received configuration data pertaining to each security check with a pre-defined or configurable network security configuration recommendation to generate a compliance result. Further, the host network element generates a compliance report by aggregating the compliance results obtained by executing each security check of the collection of security checks.Type: GrantFiled: March 19, 2019Date of Patent: August 23, 2022Assignee: Fortinet, Inc.Inventors: Robert A. May, Tarlok Birdi
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Patent number: 11412016Abstract: Systems and methods for demonstrating network security products in a virtual conference and providing training to attendees of a network security training session in the virtual conference through the use of gamification are provided. A server generates a dedicated virtual environment for a particular attendee. A three-dimensional (3D) user interface for the virtual conference is presented on a display of the particular attendee, which represents a simulated conference environment with each network security product being demonstrated as a virtual booth represented in the conference environment. A game client causes the particular attendee to navigate in the 3D user interface to a first virtual booth to access a first learning objective relating to demonstration of a first network security product corresponding to the first booth. A progress report, which is maintained by the server, is used to notify regarding other learning objectives that are of potential interest to the particular attendee.Type: GrantFiled: June 29, 2020Date of Patent: August 9, 2022Assignee: Fortinet, Inc.Inventors: Robert A. May, Jordan E. Thompson, Jamie Pate
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Patent number: 11393766Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.Type: GrantFiled: June 17, 2020Date of Patent: July 19, 2022Assignee: Intel CorporationInventors: Aleksandar Aleksov, Adel A. Elsherbini, Kristof Darmawikarta, Robert A. May, Sri Ranga Sai Boyapati
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Publication number: 20220223527Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.Type: ApplicationFiled: April 4, 2022Publication date: July 14, 2022Inventors: Kristof DARMAWIKARTA, Hiroki TANAKA, Robert MAY, Sameer PAITAL, Bai NIE, Jesse JONES, Chung Kwang Christopher TAN