Abstract: An assembly may include a fitting, a first pipe, and a first seal. The fitting may include an annular body having a first insertion end and an inner diametrical surface having a first knurled portion disposed adjacent the first insertion end. The first pipe may include a first end portion that is received into the first insertion end of the body and an outer diametrical surface including knurls formed thereon. The knurls of the outer diametrical surface may engage the first knurled portion of the fitting. The first seal element may be disposed within the fitting and may sealingly engage the first pipe and the fitting body. The engagement between the inner diametrical surface of the fitting and the outer diametrical surface of the pipe may a press fit and/or an interference fit.

Abstract: A dosimeter for radiation fields is described. The dosimeter includes a scintillator a light pipe having a first end in optical communication with the scintillator and a light detector. The light pipe may have a hollow core with a light reflective material about the periphery of the hollow core. The dosimeter may further include a light source that generates light for use as a calibrating signal for a measurement signal and/or for use to check the light pipe.

Abstract: A dosimeter for radiation fields is described. The dosimeter includes a scintillator a light pipe having a first end in optical communication with the scintillator and a light detector. The light pipe may have a hollow core with a light reflective material about the periphery of the hollow core. The dosimeter may further include a light source that generates light for use as a calibrating signal for a measurement signal and/or for use to check the light pipe.

Abstract: A dosimeter for radiation fields is described. The dosimeter includes a scintillator a light pipe having a first end in optical communication with the scintillator and a light detector. The light pipe may have a hollow core with a light reflective material about the periphery of the hollow core. The dosimeter may further include a light source that generates light for use as a calibrating signal for a measurement signal and/or for use to check the light pipe.

Abstract: A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up.

Abstract: A hermetic encapsulation and to a method of producing the same is provided. The hermetic encapsulation comprises a polymeric material disposed about a device component and has one or more plasma activated surfaces directly bonded to one another to hermetically seal the component within the material.

Abstract: A memory system circuit and method therefor are disclosed. The circuit is adapted to detect a transition in a data timing signal from an indeterminate logic level to a selected one of a high logic level and a low logic level. The circuit includes a comparator having a first input, a second input and an output. The first and second inputs receive the data timing signal and a reference voltage respectively. The output changes logic levels in response to a change in polarity of a voltage difference between the voltage of the timing signal and the reference voltage. The reference voltage is sufficiently closer to the selected one of the logic levels as compared to the other of the logic levels so as to at least substantially prevent potential false positive detections.

Abstract: A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up.

Abstract: A dosimeter for radiation fields is described. The dosimeter includes a scintillator a light pipe having a first end in optical communication with the scintillator and a light detector. The light pipe may have a hollow core with a light reflective material about the periphery of the hollow core. The dosimeter may further include a light source that generates light for use as a calibrating signal for a measurement signal and/or for use to check the light pipe.

Abstract: A memory system circuit and method therefor are disclosed. The circuit is adapted to detect a transition in a data timing signal from an indeterminate logic level to a selected one of a high logic level and a low logic level. The circuit includes a comparator having a first input, a second input and an output. The first and second inputs receive the data timing signal and a reference voltage respectively. The output changes logic levels in response to a change in polarity of a voltage difference between the voltage of the timing signal and the reference voltage. The reference voltage is sufficiently closer to the selected one of the logic levels as compared to the other of the logic levels so as to at least substantially prevent potential false positive detections.

Abstract: A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up.

Abstract: A dosimeter (100) for radiation fields is described. The dosimeter includes a scintillator (1) a light pipe (2) having a first end in optical communication with the scintillator (1) and a light detector (6). The light pipe (2) may have a hollow core (3) with a light reflective material about the periphery of the hollow core (3). The dosimeter (100) may further include a light source (61) that generates light for use as a calibrating signal for a measurement signal and/or for use to check the light pipe (2).

Abstract: A memory system circuit and method therefor are included. The circuit is adapted to detect a transition in a data timing signal from an indeterminate logic level to a selected one of a high logic level and a low logic level. The circuit includes a comparator having a first input, a second input and an output. The first and second inputs receive the data timing signal and a reference voltage respectively. The output changes logic levels in response to a change in polarity of a voltage difference between the voltage of the timing signal and the reference voltage. The reference voltage is sufficiently closer to the selected one of the logic levels as compared to the other of the logic levels so as to at least substantially prevent potential false positive detections.

Abstract: A system and method for searching and deleting segmented wide word entries in a CAM array is disclosed. A normal CAM search operation is executed to find the first word segment of a wide word. Once found, a search and delete operation is executed to find all successive word segments of the wide word, with the last word segment being marked as a deleted word segment, along a first CAM array direction. Once the last word segment is deleted, the wide word is considered to have been deleted because subsequent searches for the wide word will not find its last word segment. A purge operation is then executed along the opposite CAM array direction to delete all the word segments of the deleted wide word. Match processing circuits in each row of the CAM array can pass search results to an adjacent row above or below it to ensure that only word segments belonging to the wide word are found in the search and delete operation and deleted in the purge operation.

Abstract: A memory system circuit and method therefor are disclosed. The circuit is adapted to detect a transition in a data timing signal from an indeterminate logic level to a selected one of a high logic level and a low logic level. The circuit includes a comparator having a first input, a second input and an output. The first and second inputs receive the data timing signal and a reference voltage respectively. The output changes logic levels in response to a change in polarity of a voltage difference between the voltage of the timing signal and the reference voltage. The reference voltage is sufficiently closer to the selected one of the logic levels as compared to the other of the logic levels so as to at least substantially prevent potential false positive detections.

Abstract: A dosimeter (100) for radiation fields is described. The dosimeter includes a scintillator (1) a light pipe (2) having a first end in optical communication with the scintillator (1) and a light detector (6). The light pipe (2) may have a hollow core (3) with a light reflective material about the periphery of the hollow core (3). The dosimeter (100) may further include a light source (61) that generates light for use as a calibrating signal for a measurement signal and/or for use to check the light pipe (2).

Abstract: A CAM system comprising a plurality of CAM devices connected in a serial cascade arrangement, the CAMs in the cascade being connected to an adjacent CAM by a respective forwarding bus, with at most a first CAM in the cascade being connected to a receive data signals from a host controller and at most a last CAM devices being coupled to forward results back to the host controller; and a send signal generation means for supplying a SEND signal to the last CAM; the SEND signal for coordinating transfer of the search result from the last CAM to the host controller, the serial cascade arrangement minimizing the number of CAMs being connected to a common forwarding bus.

Abstract: A disk drive includes a slider assembly and a controller that directs current to the slider assembly to dynamically adjust the head-to-disk spacing. In one embodiment, the slider assembly includes a write element having a first end, a second end and an intermediate section, a conductor that is connected to the intermediate section. In this embodiment, the controller directs electrical current through the conductor to heat the write element without writing data to a storage disk. The electrical current can be directed through the conductor at any time prior to data transfer or during data transfer. Heating the write element causes a deformation of the slider assembly to decrease the head-to-disk spacing. In another embodiment, the slider assembly includes a separate slider deformer. Electrical current is selectively directed to the slider deformer to cause a deformation of the slider assembly to obtain a desired head-to-disk spacing.

Abstract: A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. A reference matchline sense circuit generates a self-timed control signal to keep the current supply turned on for a predetermined duration of time. Sensed data on the matchlines are latched after the current source is turned off and the matchlines are precharged to ground. Because the matchline sense circuit of the present invention precharges the matchlines to ground instead of the supply voltage, VDD, less power is consumed. By sensing the rise of the matchline voltage to an n-channel transistor threshold potential, the matchline sensing operation speed is increased.

Abstract: A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.