Abstract: An input buffer circuit is implemented in a compound semiconductor technology such as Gallium Arsenide and converts silicon semiconductor logic levels such as those produced by CMOS and TTL integrated circuits and converts them to logic levels compatible with circuits manufactured in compound semiconductor technology. The input buffer employs a balanced input circuit designed to produce an output voltage representing the switch-point of the compound semiconductor technology when the voltage received from a silicon semiconductor circuit equals the switch-point of the silicon semiconductor circuit. Otherwise, the output voltage of the input buffer is proportional to the difference between the voltage received from the silicon semiconductor circuit and the switch-point of the silicon semiconductor circuit. The balanced input circuit minimizes variations in its output voltage due to variations in power supply voltage, circuit temperature and process parameters.

Abstract: A method and apparatus for implementing silicon logic interface protocols in compound semiconductor technology converts the voltages corresponding to standard logic digital values to voltages appropriate to these digital values in compound semiconductor technology, and vice versa. In an input buffer circuit of the present invention, the voltage of the converted logic level depends only on the difference between the input standard voltage level and a reference voltage which corresponds to the threshold voltage of silicon logic so that the converted voltage is independent of device process, circuit temperature, and power supply output variations to first order. A source follower input is used so that the driving logic circuit need not source current to or sink current from the input buffer circuit so that fanout is not limited.

Abstract: A circuit for controlling clock skew has a plurality of delay elements placed in each of the clock output paths in a clock distribution circuit. The delay elements may be selectively switched into or out of each clock output path in order to adjust the delays of each clock output path so that the skew between clock outputs is minimized. The delay in each clock output path is determined by measuring the frequency of a ring oscillator created by connecting a feedback loop across the delay elements. The frequency of oscillation is measured as delay elements are switched into or out of each clock output path until the frequency reaches close to a target frequency.