Abstract: A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.

Abstract: An apparatus and method for accessing a memory. A source address that includes a page address and a page offset is received. The page address requires translation in order to form a first address that can be used to transfer data from a row of memory cells into a sense amplifier array in a memory. The page address is compared to contents of one or more page registers to determine if the data is present in the sense amplifier array as a result of a previous memory access. A second address is asserted to access a portion of the data if the data is determined to be present in the sense amplifier array.

Abstract: An apparatus and method for selecting a row of memory devices. A row value that indicates one of a plurality of chip select signals is stored in a storage element that is associated with a first address. A memory access request is received that includes the first address. The one of the plurality of chip select signals indicated by the row value is asserted to select one of a plurality of rows of memory devices.

Abstract: A page closing method and apparatus for multi-port host bridges. According to a method disclosed, a plurality of memory access commands are received from a plurality of command ports. A command is selected from one of the command ports to be the next memory access command executed. A number of pages of memory are closed in response to the command selected as the next memory access command. The number of pages closed is determined at least in part on which command port provides the next memory access command.

Abstract: A method and apparatus for accessing a memory resource, such as an array of DRAM modules, is described. The methodology commences with the receipt of a memory address during a memory access cycle. A row address is then generated by selecting predetermined bits of the memory address as the row address. Concurrently with the generation of the row address, a determination is made as to the configuration of a memory device within the memory resource and targeted by the memory address. Thereafter, a column address is generated by selecting bits of the memory address as the column address based on the configuration of the targeted memory device. The time required for the determination of the configuration of the targeted memory device is thus absorbed within the time expended generating the row address.

Abstract: A queue structure for transmitting a multiple-bit signal from a first sub-system operating in a first clocking domain in a computer system to a second sub-system operating in a second clocking domain in the computer system is disclosed. The queue structure comprises a queue data latch having a plurality of storage elements, wherein each of the plurality of storage elements can store the multiple-bit signal from the first sub-system. A load pointer is used for generating a first multiple-bit count indicating one of the plurality of storage element for storing the multiple-bit signal. A synchronization unit is coupled to the load pointer for receiving the first multiple-bit count. The synchronization unit outputs the multiple-bit count at the second sub-system when the multiple-bit signal is ready to be sampled in the second clocking domain.

Abstract: In a computer system processing out of order commands, a method for detecting situations in which errors could be caused by execution of an out of order command. The method includes the steps of receiving a first address of a first type and receiving a next address of the first type. Information is accumulated regarding differences between the first address and the next address. The method also includes receiving an address of a second type and using the accumulated information to determine whether the address of the second type is an address associated with a command whose execution can create a hazard. A hazard indication is generated if it is determined that the address of the second type is an address associated with a command whose execution can create a hazard. In one embodiment, the first type of address is an address associated with a first type of command and the second type of address is an address associated with a second type of command.

Abstract: A novel method for performing memory accesses. Falling edges of a column address strobe (CAS) signal are used to cause dynamic random access memories (DRAMs) to drive data corresponding to the current address onto a data bus coupled to the input of a set of latches. A memory latch data (MLAD) signal is used to enable the set of latches. When the MLAD signal is asserted, the latches latch the data at the input in response to a falling edge of the CAS signal. When the MLAD signal is deasserted, the latch does not latch the data at the input in response to the falling edge of the CAS signal. Since the same signal (CAS) is used to control when the data is driven by the DRAMs and when the data is latched by the latches, the differences in output timings, signal path delays, and loads are avoided. The use of expensive timing compensation circuits and special tuning of these circuits for each circuit board redesign is thereby avoided.

Abstract: A method and apparatus for transferring data from a first bus to a second bus. A bridge couples a first bus to a second bus. The bridge includes a buffer to store two data elements of a first packet transferred to the buffer from the first bus. The bridge also includes a controller that permits a first data element to be transferred from the buffer to the second bus. In addition, if at least a portion of a second packet has not been transferred to the bridge from the first bus, then the controller causes at least one wait state to be inserted on the second bus before transferring the second data element of the first packet from the buffer to the second bus.

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer.

Abstract: A memory configuration system including a memory controller comprising a set of memory configuration registers which store information related to memory devices installed in random access memory. The memory configuration registers correspond to one or more rows of memory banks in the random access memory. The memory controller also includes a row size and mask generator coupled to the memory configuration register set and a memory configuration decoder coupled to the row size and mask generator. The combination of logic within the row size and mask generator and the memory configuration decoder is used to generate a base address for each row of memory locations within the random access memory. The present invention automatically reconfigures the memory array to define the most populous row as Row 0 regardless of where the largest row is physically populated. This reconfiguration of the memory array is the logical to physical mapping feature provided by the present invention.

Abstract: A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of devices is described. The memory controller apparatus interfaces the microprocessor and the plurality of devices. The microprocessor functions asynchronously with the plurality of devices. The memory controller apparatus comprises a delay line circuitry coupled to receive a selected request for accessing the memory array from one of the microprocessor and the plurality of devices, the delay line means further including means for generating a plurality of memory timing control signals. The memory timing control signals are used for accessing the memory array. The delay line circuitry functions independently of any clock signal. The delay line circuitry is only triggered by the selected request. The memory controller apparatus further comprises a memory state circuitry coupled to the delay line circuitry for controlling sequence and timing of the memory timing control signals.

Abstract: A data processing system which includes a central processor unit which has an arithmetic logic unit (ALU) for performing fixed point arithmetic operations and a separate floating point unit (FPU) for performing floating point operations and which uses multi-level microcode architecture wherein each unit has its own control store (a "horizontal" store) which responds to addresses of execution control signals supplied thereto from a common control store (a "vertical" store) to produce horizontal microinstructions for performing ALU and FPU operations, respectively. Selected ones of such addresses are recognized for ALU operations by the CPU control store only, other selected ones are recognized for FPU operations by the FPU control store only, while still other selected ones are recognized for both ALU and FPU operations by both control stores so that such operations can be performed simultaneously in parallel.

Abstract: Spaced hollow vertical posts are supported by base means. Each post has a pair of spaced substantially coextensive vertically elongated flat panel bars of substantial thickness with vertical opposite side edges and a series of vertically spaced shelf bracket connection apertures intermediate the edges, there being a pair of substantially coextensive vertical opposite side channel members of relatively thin gauge material to which the side edges of the panel bars are secured in edgewise abutment. Stabilizing bar means have angular attachment terminal tongues or vertical finishing strips may be engaged with transverse attachments straps on the channels. Gusset members in the base structure support the posts and are formed from horizontally elongated vertically standing panels having plate attachment structure at their ends. The base includes detachable shelf and trim structure.