Patents by Inventor Robert Nicholas Hilton

Robert Nicholas Hilton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10203911
    Abstract: A multi-processor system with a portion of content-addressable memory (CAM) configured as a tuple space to control data flow between processing element. A writing processor may write to a tuple space followed by a reading processor reading from the tuple space. However the system may control access to the tuple space so that no read operations may be performed for a particular tuple space before that space is written to. Further, no write operations may be performed to the tuple space prior to previous written data being read from the tuple space. A processor wishing to use the tuple space before being permitted to do so may be stalled, thus controlling data flow between operating processors.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: February 12, 2019
    Assignee: Friday Harbor LLC
    Inventors: Ricardo Jorge Lopez, Ramon Zuniga, Robert Nicholas Hilton
  • Publication number: 20180088904
    Abstract: A semiconductor chip with a first processing element, a state machine, a first read first-in first-out (FIFO) memory component, and a second read FIFO memory component. The state machine receives a request from the first processing element for a first value from the first read FIFO memory component and a second value from the second read FIFO memory component. The first processing element may change from an active state to a second state after submitting the read request. The state machine may determine if the first and the second FIFO memory components have data. The first processing element changes back to the active state after the state machine transfers the first and second values to registers.
    Type: Application
    Filed: September 26, 2016
    Publication date: March 29, 2018
    Applicant: KNUEDGE, INC.
    Inventors: Ricardo Jorge Lopez, Ramon Zuniga, Robert Nicholas Hilton, Don Yokota
  • Patent number: 9870785
    Abstract: Features that may be computed from a harmonic signal include a fractional chirp rate, a pitch, and amplitudes of the harmonics. A fractional chirp rate may be estimated, for example, by computing scores corresponding to different fractional chirp rates and selecting a highest score. A first pitch may be computed from a frequency representation that is computed using the estimated fractional chirp rate, for example, by using peak-to-peak distances in the frequency distribution. A second pitch may be computed using the first pitch, and a frequency representation of the signal, for example, by using correlations of portions of the frequency representation. Amplitudes of harmonics of the signal may be determined using the estimated fractional chirp rate and second pitch. Any of the estimated fractional chirp rate, second pitch, and harmonic amplitudes may be used for further processing, such as speech recognition, speaker verification, speaker identification, or signal reconstruction.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 16, 2018
    Assignee: KnuEdge Incorporated
    Inventors: David Carlson Bradley, Yao Huang Morin, Massimo Mascaro, Janis I. Intoy, Sean Michael O'Connor, Ellisha Natalie Marongelli, Robert Nicholas Hilton
  • Publication number: 20170337295
    Abstract: A multi-processor system with a portion of content-addressable memory (CAM) configured as a tuple space to control data flow between processing element. A writing processor may write to a tuple space followed by a reading processor reading from the tuple space. However the system may control access to the tuple space so that no read operations may be performed for a particular tuple space before that space is written to. Further, no write operations may be performed to the tuple space prior to previous written data being read from the tuple space. A processor wishing to use the tuple space before being permitted to do so may be stalled, thus controlling data flow between operating processors.
    Type: Application
    Filed: May 18, 2016
    Publication date: November 23, 2017
    Inventors: Ricardo Jorge Lopez, Ramon Zuniga, Robert Nicholas Hilton
  • Publication number: 20170147513
    Abstract: A shared program memory and related components configured to distribute data from a memory block to multiple processors at the same time. An arbiter determines what processors are requesting data from the same memory locations. Data from that memory location is then accessed and sent to the requesting processors so that the data arrives at about the same time to each processor, for example, during the same clock cycle. Such distribution is made possible using a configuration such as a shared data bus with corresponding valid bits for each register or using a multicaster and separate data busses for each processor.
    Type: Application
    Filed: November 24, 2015
    Publication date: May 25, 2017
    Applicant: KNUEDGE, INC.
    Inventors: Robert Nicholas Hilton, William Christensen Clevenger, Jerome V. Coffin
  • Patent number: 6164485
    Abstract: A container lid (10) including a base (11) having a rim (13) adapted to fit onto a container, a raised section projecting above the rim, the raised section including an inverted recess (15), a domed cover (12) attached to the raised section (14) above the recess to create a compartment (24) within and of substantially the same depth as the container lid, and releasable sealing means between the cover and the raised section to provide access to the compartment.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: December 26, 2000
    Assignee: Promotions Factory (Aust) PTY LTD
    Inventor: Robert Nicholas Hilton