Abstract: On-die functional blocks may use multiple communication networks to send requests and receive responses. For example, a first functional block may send a request via a first network. In response to receiving the request, a second functional block may respond to the first functional block via a second network. The second functional block may also send any requested data to the first functional block via a third network.

Abstract: Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit.

Abstract: A method for communication among multiple on-die functional blocks using multiple communication networks is disclosed. The method may include sending a request from a first functional block via a first network. In response to receiving the request, a second functional block may respond to the first functional block via a second network. The second functional block may also send any requested data to the first functional block via a third network.

Abstract: A method for communication among multiple on-die functional blocks using multiple communication networks is disclosed. The method may include sending a request from a first functional block via a first network. In response to receiving the request, a second functional block may respond to the first functional block via a second network. The second functional block may also send any requested data to the first functional block via a third network.

Abstract: Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit.

Abstract: In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit.

Abstract: A multi-layer full dense mesh (MFDM) device. The MFDM may include a metal-top layer including a bump pad array that may include a power1 (PWR1) bump pad within a PWR1 bump region, a VSS bump pad within a VSS bump region, and a power2 (PWR2) bump pad within a PWR2 bump region. The metal-top layer may also include a PWR1 majority metal-top region. The MFDM may also include a metal-top-1 layer beneath the metal-top layer and including a VSS majority metal-top-1 region, a PWR1 metal-top-1 region, and a PWR2 metal-top-1 region. The MFDM may also include a metal-top-2 layer beneath the metal-top-1 layer and including a PWR2 majority metal-top-2 region, a VSS metal-top-2 region, and a PWR1 metal-top-2 region. The MFDM may also include top-1 VIAs disposed between the metal-top layer and the metal-top-1 layer, and top-2 VIAs disposed between the metal-top-1 layer and the metal-top-2 layer.

Abstract: An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality.

Abstract: A multi-layer full dense mesh (MFDM) device. The MFDM may include a metal-top layer including a bump pad array that may include a power1 (PWR1) bump pad within a PWR1 bump region, a VSS bump pad within a VSS bump region, and a power2 (PWR2) bump pad within a PWR2 bump region. The metal-top layer may also include a PWR1 majority metal-top region. The MFDM may also include a metal-top-1 layer beneath the metal-top layer and including a VSS majority metal-top-1 region, a PWR1 metal-top-1 region, and a PWR2 metal-top-1 region. The MFDM may also include a metal-top-2 layer beneath the metal-top-1 layer and including a PWR2 majority metal-top-2 region, a VSS metal-top-2 region, and a PWR1 metal-top-2 region. The MFDM may also include top-1 VIAs disposed between the metal-top layer and the metal-top-1 layer, and top-2 VIAs disposed between the metal-top-1 layer and the metal-top-2 layer.

Abstract: A cross point switch, in accordance with one embodiment, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.

Abstract: Embodiments of the invention provide low-noise arrangements for very-large-scale integration (VLSI) differential input/output (I/O) structures (I/O pins, solder bumps, vias, etc.). Novel geometries are described for arranging differential pairs of I/O structures in perpendicular or near-perpendicular “quads.” The geometries effectively place one differential pair on or near the perpendicular bisector of its adjacent differential pair, such that field cancellation and differential reception can substantially eliminate noise without the need for added spacing or shields. By exploiting these effects, embodiments can suppress noise, independent of I/O structure spacing, and arbitrarily small spacings are permitted. Such arrangements can be extended into running chains, and even further into arrays of parallel chains. The parallel chains can be separated by supply structures (e.g.

Abstract: A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is configured to select one of its inputs to be coupled to the output. A control circuit is configured to cause the multiplexer to sequentially select outputs of the M+1 latches responsive to N successive clock pulses, and further configured to cause the M+1 latches to sequentially latch data received through the common data input.

Abstract: Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit.

Abstract: An apparatus and method for encoding data are disclosed that may allow for variable run length encoding of data to be transmitted. An ordered stream of data bits is received from a logic circuit, and N sequential data bits of the stream are selected, where N is a positive integer. Of the N sequential data bits, M sequential data bits are selected, wherein M is a positive integer less than N. The M sequential data bits are then encoded to generate a code word that includes P data bits, wherein P is a positive integer greater than M and less than N. The code word is then concatenated with a subset of the N sequential data bits that excludes the M sequential data bits to form a transmission word. A transmit unit then sends the data bits of the transmission word in a serial fashion.

Abstract: An apparatus and method for encoding data are disclosed that may allow for variable run length encoding of data to be transmitted. An ordered stream of data bits is received from a logic circuit, and N sequential data bits of the stream are selected, where N is a positive integer. Of the N sequential data bits, M sequential data bits are selected, wherein M is a positive integer less than N. The M sequential data bits are then encoded to generate a code word that includes P data bits, wherein P is a positive integer greater than M and less than N. The code word is then concatenated with a subset of the N sequential data bits that excludes the M sequential data bits to form a transmission word. A transmit unit then sends the data bits of the transmission word in a serial fashion.

Abstract: Embodiments of an apparatus and method for encoding data are disclosed that may allow for reduced simultaneous switching output noise. The apparatus may include a row decode circuit, a column decode circuit, and a memory array. The row decode circuit and column decode circuits may be configured to decode a first portion and a second portion, respectively, of a given data word of a first plurality of data words, where each data word may include N data bits, and where N is an integer greater than one. The memory array may be configured to store a second plurality of data words where each data word may include M data bits, and where M is an integer greater than N. The memory array may be further configured to retrieve a given data word of the second plurality of data words dependent upon the decoded first and second portions.

Abstract: Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit.

Abstract: An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality.

Abstract: Embodiments of the invention provide low-noise arrangements for very-large-scale integration (VLSI) differential input/output (I/O) structures (I/O pins, solder bumps, vias, etc.). Novel geometries are described for arranging differential pairs of I/O structures in perpendicular or near-perpendicular “quads.” The geometries effectively place one differential pair on or near the perpendicular bisector of its adjacent differential pair, such that field cancellation and differential reception can substantially eliminate noise without the need for added spacing or shields. By exploiting these effects, embodiments can suppress noise, independent of I/O structure spacing, and arbitrarily small spacings are permitted. Such arrangements can be extended into running chains, and even further into arrays of parallel chains. The parallel chains can be separated by supply structures (e.g.

Abstract: A cross point switch, in accordance with one embodiment, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.