Abstract: An improved sampling network analyzer is described, in which a stored memory, for example, a programmable read-only memory (PROM), is utilized to store the discrepancies between various predetermined mid-band voltage gains and their desired, exact values, and to supply this correction information to the sampling network analyzer in order to produce a more accurate amplitude measure of the amplitude of voltages applied to the inputs of the sampling network analyzer. In addition, low- and high-frequency characteristic frequencies can be stored, and correction made for the gain-vs-frequency characteristic of an amplifier or amplifier chain. The correction factors are typically measured in final test of the sampling network analyzer, and programmed into a PROM that is incorporated into the particular sampling network analyzer.

Abstract: An improved Sampling Network Analyzer is disclosed, in which synchronization of the sampling of one or more input signals, either voltages or currents, is effected by means of a phase-locked loop (PLL). A reference signal serves to synchronize a phase-locked loop, which in turn synchronizes sample-and-hold circuits utilized for measurement. A C preset counter permits the operator to set a desired number of samples per measurement. A Y preset counter maintains the voltage-controlled oscillator within a predetermined (relatively narrow) range of frequencies. Operation of the sample-and-hold circuits is at a frequency that is related to the reference frequency by the ratio of two integers. A D preset counter is provided in the reference signal path to allow the Sampling Network Analyzer to be synchronized to a subharmonic of the reference frequency where the reference frequency is too high to permit the desired number of samples per measurement within a single period.