Abstract: A valve control system includes a rotatable valve operably coupled to a motor, a valve position indicator configured to rotate with the rotatable valve, at least two sensing devices configured to detect the valve position indicator, and a controller. The at least two sensing devices include a home position sensing device and an end-of-travel position sensing device. The controller includes valve state determination logic having circuitry configured to monitor a status of a home indicator and an end-of-travel indicator of the rotatable valve, determine a commanded direction of movement of the rotatable valve, monitor the status of the home indicator and the end-of-travel indicator before a valve rotation stop is commanded and after the valve rotation stop is commanded, and determine a current state of the rotatable valve based on the commanded direction of movement and at least one of the status of the home indicator and the end-of-travel indicator.

Abstract: Methods and systems for operating internal systems of a vehicle are provided. Aspects include providing a field programmable gate array (FPGA), the FPGA including a communication channel port, wherein the communication channel port is operable to connect to one or more systems through a communication channel, and wherein the FPGA is configured to operate in one or more control modes, receiving a communication channel input to the communication channel port of the FPGA, based at least in part on the communication channel input, determining a control mode from the one or more control modes, and operating the FPGA in the control mode, wherein the control mode is associated with one system of the one or more systems.

Abstract: Diagnosing whether controllers of internal vehicle systems are the source of failures detected by a system control managing a vehicle such as a spacecraft. Highspeed data is received via at a field programmable gate array (FPGA) embedded in an assembly of the vehicle. The FPGA includes a controller and a digital diagnostic interface. In one embodiment, the diagnostic interface utilizes Very Highspeed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) for performance modeling of a controller configured to control at least one internal system within the vehicle. The VHDL performance models the controller. Upon receiving an indication of a failure, the performance modeling of the controller is used to ascertain whether or not the controller is the source of the failure. Disassembly of the assembly housing the internal system is not required in order to ascertain whether or not the controller is the source of the failure.

Abstract: Providing collision avoidance protection to controllers sharing the same sensor. Each of a pair of asynchronous controllers changes the period of a sync pulse transmitted to the other controller to indicate to the other controller it is synchronized. When one of the controllers begins reading data from the shared sensor, the other controller waits to receive another sync pulse for indicating when the controller is finished reading data from the shared sensor. Thus, the asynchronous controllers avoid accessing the same sensor at the same time.

Abstract: Diagnosing whether controllers of internal vehicle systems are the source of failures detected by a system control managing a vehicle such as a spacecraft. Highspeed data is received via at a field programmable gate array (FPGA) embedded in an assembly of the vehicle. The FPGA includes a controller and a digital diagnostic interface. In one embodiment, the diagnostic interface utilizes Very Highspeed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) for performance modeling of a controller configured to control at least one internal system within the vehicle. The VHDL performance models the controller. Upon receiving an indication of a failure, the performance modeling of the controller is used to ascertain whether or not the controller is the source of the failure. Disassembly of the assembly housing the internal system is not required in order to ascertain whether or not the controller is the source of the failure.

Abstract: Methods and systems for operating internal systems of a vehicle are provided.

Abstract: Providing collision avoidance protection to controllers sharing the same sensor. Each of a pair of asynchronous controllers changes the period of a sync pulse transmitted to the other controller to indicate to the other controller it is synchronized. When one of the controllers begins reading data from the shared sensor, the other controller waits to receive another sync pulse for indicating when the controller is finished reading data from the shared sensor. Thus, the asynchronous controllers avoid accessing the same sensor at the same time.

Abstract: A computer-implemented method for performing stability analysis for a digital motor controller includes receiving a reference signal to be injected into a digital speed control loop and controlling, by a hardware description language (VHDL) component, the injection of the reference signal into the digital control loop through a field programmable gate array (FPGA) hardware interface. The method also includes providing the reference signal to the digital speed control loop to determine a performance of the digital motor controller and receiving a feedback signal, at the FPGA hardware interface, from the digital speed control loop based on the reference signal. The method includes comparing the reference signal to the feedback signal to evaluate the performance of the digital motor controller and exporting a result of the comparing by the FPGA hardware interface to indicate the performance of the digital motor controller.

Abstract: An electromechanical system has a component to be positioned, a rotary permanent magnet motor for positioning the component, and sensors for determining an apparent position of the component based upon rotation of the permanent magnets. A control counts movement of the permanent magnets that pass the sensors in a desired direction and also in an undesired direction. The control reaches an actual position of the component based upon both directions of rotation. The control also compares the actual position to an expected position of the component and identifies a need to calibrate should a difference between the actual and expected positions differ by more than a determined amount. A method is also disclosed.

Abstract: A counter is started on the falling edge of a tach pulse. This counter counts to the rising edge of a second tach pulse, such as the next tach pulse. During the duration of the tach pulse the FPGA calculates the RPM of a motor. In this way, during each commutation period, a RPM is calculated. The present system performs a RPM calculation during each commutation period and/or tach pulse duration.

Abstract: A computer-implemented method for performing stability analysis for a digital motor controller includes receiving a reference signal to be injected into a digital speed control loop and controlling, by a hardware description language (VHDL) component, the injection of the reference signal into the digital control loop through a field programmable gate array (FPGA) hardware interface. The method also includes providing the reference signal to the digital speed control loop to determine a performance of the digital motor controller and receiving a feedback signal, at the FPGA hardware interface, from the digital speed control loop based on the reference signal. The method includes comparing the reference signal to the feedback signal to evaluate the performance of the digital motor controller and exporting a result of the comparing by the FPGA hardware interface to indicate the performance of the digital motor controller.

Abstract: A system for detecting sensor failure and/or operating with a failed sensor in an electrical machine includes an electrical machine, three or more sensors configured to connect to the electrical machine, and a sensor module operatively connected to each sensor to receive sensor signals from the sensors. The sensor module includes a failure detection module operatively connected to each sensor and configured to determine if each sensor is a failed sensor or a functioning sensor. The sensor module also includes a virtual sensor module operatively connected to the failure detection module and configured to output simulated sensor signals for the failed sensor, wherein the sensor module is configured to output the sensor signals for each functioning sensor. The system includes a control module operatively connected to the sensor module and the electrical machine to receive sensor signals and simulated sensor signals to control operation of the electrical machine.

Abstract: A system for detecting sensor failure and/or operating with a failed sensor in an electrical machine includes an electrical machine, three or more sensors configured to connect to the electrical machine, and a sensor module operatively connected to each sensor to receive sensor signals from the sensors. The sensor module includes a failure detection module operatively connected to each sensor and configured to determine if each sensor is a failed sensor or a functioning sensor. The sensor module also includes a virtual sensor module operatively connected to the failure detection module and configured to output simulated sensor signals for the failed sensor, wherein the sensor module is configured to output the sensor signals for each functioning sensor. The system includes a control module operatively connected to the sensor module and the electrical machine to receive sensor signals and simulated sensor signals to control operation of the electrical machine.

Abstract: A system includes a first control system configured to operate at a first clock speed, a second control system configured to provide an output to the first control system and configured to operate at a second clock speed different from the first clock speed, and a synchronization module operatively connecting the first control module to the second control module and configured to synchronize the first control system and the second control system such that the output of the second control system is timed to synchronize with the first clock speed.

Abstract: A sensorless motor controller includes a variable link control, including a radiation-hardened field programmable gate array (FPGA) and a back electromotive force (EMF) decoder circuit. The back EMF decoder infers the position of a rotor of the motor. A filter on the decoder conditions the back EMF signal and has multiple cutoff frequencies which can be dynamically controlled by the FPGA in order to compensate for phase shift in the back EMF signal. The FPGA also controls a variable DC link and its digital speed control loop.

Abstract: A system includes a first control system configured to operate at a first clock speed, a second control system configured to provide an output to the first control system and configured to operate at a second clock speed different from the first clock speed, and a synchronization module operatively connecting the first control module to the second control module and configured to synchronize the first control system and the second control system such that the output of the second control system is timed to synchronize with the first clock speed.

Abstract: As each tach pulse time duration is known a priori, it may be utilized by a system to an advantage. A counter may be started on the falling edge of a tach pulse. This counter may count to the rising edge of a second tach pulse, such as the next tech pulse. During the duration of the tach pulse the FPGA may calculate the RPM of a motor. In this way, during each commutation period, a RPM may be calculated. In contrast to legacy systems where a RPM calculation may have been performed every other tach pulse, the present system may perform a RPM calculation during each commutation period and/or tach pulse duration. Stated another way, the calculation of the delta of the commutation period less the tach pulse duration may be determined while the counter is idle.

Abstract: A sensorless motor controller includes a variable link control, including a radiation-hardened field programmable gate array (FPGA) and a back electromotive force (EMF) decoder circuit. The back EMF decoder infers the position of a rotor of the motor. A filter on the decoder conditions the back EMF signal and has multiple cutoff frequencies which can be dynamically controlled by the FPGA in order to compensate for phase shift in the back EMF signal. The FPGA also controls a variable DC link and its digital speed control loop.

Abstract: A compact field programmable gate array (FPGA)-based digital motor controller (102), a method, and a design structure are provided. The compact FPGA-based digital motor controller (102) includes a sensor interface (206) configured to receive sensor data from one or more sensors (104) and generate conditioned sensor data. The one or more sensors (104) provide position information for a DC brushless motor (108). The compact FPGA-based digital motor controller (102) also includes a commutation control (210) configured to create switching commands to control commutation for the DC brushless motor (108). The commutation control (210) generates commutation pulses from the conditioned sensor data of the sensor interface (206). The compact FPGA-based digital motor controller (102) also includes a time inverter (208) configured to receive the commutation pulses.

Abstract: A compact field programmable gate array (FPGA)-based digital motor controller (102), a method, and a design structure are provided. The compact FPGA-based digital motor controller (102) includes a sensor interface (206) configured to receive sensor data from one or more sensors (104) and generate conditioned sensor data. The one or more sensors (104) provide position information for a DC brushless motor (108). The compact FPGA-based digital motor controller (102) also includes a commutation control (210) configured to create switching commands to control commutation for the DC brushless motor (108). The commutation control (210) generates commutation pulses from the conditioned sensor data of the sensor interface (206). The compact FPGA-based digital motor controller (102) also includes a time inverter (208) configured to receive the commutation pulses.