Abstract: A peripheral device selected with a chip select is mapped onto address space occupied by DRAM without causing internal or external contentions. A first address range is provided for accessing DRAM. A second address range is provided for accessing another device. The second address range is within the first address range. A row address strobe is provided for accesses within both the first and second address ranges but the column address strobe to the DRAM is inhibited when a memory access occurs within the second address range.

Abstract: Each of a plurality of output circuits is coupled with one pair of a plurality of pairs of adjacent odd and even bits of a sequential group of address bits. The output circuits provide an address bus with the odd address bits during a first time period and with the even address bits during a second time period. The odd address bits are provided as a column address (or a row address) and the even address bits are provided as the row address (or column address).

Abstract: A DRAM controller is incorporated onto an existing microcontroller architecture. Existing chip select signals or other signals on the microcontroller are multiplexed with RAS and CAS signals. The RAS and CAS signals are asserted when an address is within a specific programmable address range and DRAM mode is enabled. The pins selected for RAS and CAS provide regular signals such as chip selects when not in DRAM mode. The timing of the chip select signal signals are adjusted when the chip select signals are utilized as column and row address strobes. Additionally, multiplexed addresses are provided from the microcontroller as well as refresh control. The microcontroller can provide high byte and low byte access by providing an upper column address strobe signal (UCAS) to support access for high byte and word access and a lower column address strobe signal (LCAS) to support low byte and word access. Mid range chip selects provide the UCAS and LCAS signals.

Abstract: A first plurality of address bits is provided to an address bus during a first time period. At least one banking address bit or at least one non banking address bit is selected according to a banking control signal, the selected bit being part a second plurality of address bits. The second plurality of address bits is multiplexed onto the address bus during a second time period. A first selector circuit receives a first and second group of address bits for a memory and outputs the first and second group during a first and second time period, respectively, according to a first select signal. A second selector circuit provides a subset of the second group to the first selector circuit, the second selector circuit selects a banking address group or a non banking address group as the subset according to a memory banking enable signal.

Abstract: A microcontroller includes an integrated memory and an integrated DMA controller. During testing, the DMA controller is used to perform read/write tests of background patterns and complements thereof to the integrated memory. The integrated memory need not contain the BIST logic typically required of integrated memories. By using the DMA controller to perform BIST-type testing, the tests are not hardware-bound. Typically, the BIST logic included in integrated memories is designed and tested during the design of the microcontroller. This design and test time is replaced by a (possibly shorter) task of generating test vectors for the requisite DMA transfers. The risk of having an error in the BIST test is reduced using the present testing method. Formerly, if BIST logic was found to be in error, new manufacturing masks for the microcontroller were required to repair the problem. A large time and monetary investment was required.