Patents by Inventor Robert Payne
Robert Payne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040040599Abstract: A method is disclosed for the manufacture of a float (30) comprising the following steps: providing a mould (10) having a first enclosure (12) opening into a second enclosure (14) of greater dimensions than the first enclosure (12), and an inlet (16) into the first enclosure (12), the first and second enclosures (12, 14) together defining the shape of the float (30); injecting a mixture comprising plastics material and blowing agent into the inlet (16), such that the mixture passes through the first enclosure (12) and then into the second enclosure (14); and causing or allowing the mixture to set, thereby forming the float (30). The float (30), the mould (10) and a fluid storage chamber (60) including the float (30) are also disclosed.Type: ApplicationFiled: May 28, 2003Publication date: March 4, 2004Inventor: Simon Robert Payne
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Patent number: 6673128Abstract: A method of sealing an end of a battery container is disclosed. The method includes: (a) providing a plurality of supports in a wall of the container toward the end of the container; (b) scoring the wall of the container at a position between the end of the container and the supports; (c) inserting a top assembly into the container such that the top assembly contacts the supports; and (d) folding an edge of the container over the top assembly.Type: GrantFiled: December 10, 2001Date of Patent: January 6, 2004Assignee: The Gillette CompanyInventors: Robert Payne, Gary M. Searle
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Patent number: 6665855Abstract: A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, the rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized subset of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.Type: GrantFiled: December 11, 2001Date of Patent: December 16, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Robert Payne, Mark Bapst, Timothy Pontius
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Publication number: 20030204831Abstract: A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, the rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized subset of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.Type: ApplicationFiled: December 11, 2001Publication date: October 30, 2003Applicant: VLSI Technology, Inc. (Koninklijke Philips Electronics N.V.)Inventors: Robert Payne, Mark Bapst, Timothy Pontius
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Publication number: 20030081713Abstract: A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.Type: ApplicationFiled: October 31, 2001Publication date: May 1, 2003Applicant: Koninklijke Philips Electronics N.V.Inventors: Timothy Pontius, Robert Payne, David Evoy
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Patent number: 6542015Abstract: A method and apparatus for correcting the duty cycle of an uncorrected differential clock signal having a sinusoidal characteristic and outputting a corrected differential square wave clock signal. In the method, the uncorrected differential clock signal is provided as an uncorrected differential current to a pair of summing nodes. A correction differential voltage is generated as a signal corresponding to the inverse of the corrected differential clock signal and having a common mode voltage of one of the correction differential signals relative to a common mode voltage of the other of the correction differential voltages that depends on the duty cycle of the uncorrected differential clock signal. A correction differential current is generated, corresponding to the correction differential voltage.Type: GrantFiled: March 28, 2001Date of Patent: April 1, 2003Assignee: Texas Instruments IncorporatedInventors: Jian Zhou, Robert Payne, Huanzhang Huang, Douglas Wente
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Publication number: 20030000149Abstract: A locking device for attachment to a fixed portion of a transit vehicle door system is for locking one or more doors of the transit vehicle door system in either a fully locked position or a pushback lock position. The locking device has a simple lock arm, biased toward the locking position and rotatably attached to the fixed portion of the transit vehicle door system at a first pivot of the rotary lock arm, the rotary lock arm having at least one door engagement portion for engaging a portion of the door(s) for locking the door(s) when the rotary lock arm is in at least one of the locking position and the pushback position thereof. A linear actuator, rotating the lock arm to the unlocked position when energized, is attached to the fixed portion of the transit vehicle door system and connected to a second pivot of the lock arm, said second pivot offset from the first pivot. A lock actuator sensing switch provides a feedback on the actuator position to the transit vehicle control system.Type: ApplicationFiled: February 19, 2002Publication date: January 2, 2003Inventors: Robert L. Oakley, Robert Payne
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Patent number: 6492046Abstract: A metal-air battery including (a) an anode, (b) a cathode, (c) a separator between the anode and the cathode, and (d) a container having at least one air access port has (e) a membrane between the cathode and the container that has a variable thickness.Type: GrantFiled: June 22, 2000Date of Patent: December 10, 2002Assignee: The Gillette CompanyInventors: Robert Payne, Gary Searle, Vance Rogers Shepard, Jr.
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Publication number: 20020140477Abstract: The duty cycle for a periodic signal such as a clock signal is idealized by feeding back duty cycle information. Duty cycle information is detected by a capacitor connected in serial with a resistor across the outputs of a feedback differential transistor pair. Over time, the capacitor will be charged or discharged when the duty cycle varies from fifty percent. The detected duty cycle information is fed back to an amplifier where the incoming clock signal is mixed with the feedback signal. The amplifier itself comprises a first differential comparator stage receiving the uncorrected clock signal, a gain stage that amplifies and level shifts the feedback signal, and a second differential pair receiving the amplified feedback signal.Type: ApplicationFiled: March 28, 2001Publication date: October 3, 2002Inventors: Jian Zhou, Robert Payne, Huanzhang Huang, Douglas Wente
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Patent number: 6423438Abstract: A method of sealing an end of a battery container is disclosed. The method includes: (a) providing a plurality of supports in a wall of the container toward the end of the container; (b) scoring the wall of the container at a position between the end of the container and the supports; (c) inserting a top assembly into the container such that the top assembly contacts the supports; and (d) folding an edge of the container over the top assembly.Type: GrantFiled: January 31, 2000Date of Patent: July 23, 2002Assignee: The Gillette CompanyInventors: Robert Payne, Gary M. Searle
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Publication number: 20020041988Abstract: A method of sealing an end of a battery container is disclosed. The method includes: (a) providing a plurality of supports in a wall of the container toward the end of the container; (b) scoring the wall of the container at a position between the end of the container and the supports; (c) inserting a top assembly into the container such that the top assembly contacts the supports; and (d) folding an edge of the container over the top assembly.Type: ApplicationFiled: December 10, 2001Publication date: April 11, 2002Applicant: The Gillette Company, a Delaware corporationInventors: Robert Payne, Gary M. Searle
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Patent number: 6347395Abstract: A rapid silicon processing arrangement significantly decreases the time from initial design to market introduction. Consistent with one embodiment of the present invention, rapid silicon processing arrangement uses a deconfigurable and extendible reference-chip development platform that includes a programmable device such as an electronically reconfigurable gate array and an off-platform bus for communicating with external devices. The reference-chip development platform can be deconfigured by deselecting communicative activity by one or more of functional block macros. The external devices can be used with the reference-chip development platform to test a hardware representation of the synthesized of the functional block macros in the programmable device within the reference-chip development platform as extended by the off-platform bus. The approach significantly decreases the development time, from initial design to market introduction.Type: GrantFiled: December 18, 1998Date of Patent: February 12, 2002Assignee: Koninklijke Philips Electronics N.V. (KPENV)Inventors: Robert Payne, Mark Bapst, Timothy Pontius
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Patent number: 6232007Abstract: A metal-air battery including (a) an anode; (b) a cathode; (c) a separator between the anode and the cathode; and (d) a container having a louver is disclosed.Type: GrantFiled: August 13, 1999Date of Patent: May 15, 2001Assignee: The Gillette CompanyInventors: Robert Payne, Gary Searle, Vance Rogers Shepard, Jr.
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Patent number: 5976943Abstract: A programmable resistor is composed of two layers. A first layer of the programmable resistor has a substantially lower resistance than a second layer of the programmable resistor. The programmable resistor is programmed by placing a signal across the programmable resistor. A resulting current generated by the signal travels in parallel through the first layer of the programmable resistor and the second layer of the programmable resistor. The voltage of the signal is of a sufficient level so that a first portion of the resulting current which travels through the first layer causes a break in the first layer of the programmable resistor. However, the voltage of the signal is not of a sufficient level to allow a second portion of the resulting current which travels through the second layer to cause a break in the second layer of the programmable resistor.Type: GrantFiled: December 27, 1996Date of Patent: November 2, 1999Assignee: VLSI Technology, Inc.Inventors: Martin Harold Manley, Robert Payne
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Patent number: 5882998Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.Type: GrantFiled: April 3, 1998Date of Patent: March 16, 1999Assignee: VLSI Technology, Inc.Inventors: Harlan Lee Sur, Jr., Subhas Bothra, Xi-Wei Lin, Martin H. Manley, Robert Payne
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Patent number: 5854510Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.Type: GrantFiled: June 26, 1997Date of Patent: December 29, 1998Assignee: VLSI Technology, Inc.Inventors: Harlan Lee Sur, Jr., Subhas Bothra, Xi-Wei Lin, Martin H. Manley, Robert Payne
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Patent number: 5221543Abstract: A process is disclosed for making a chewing gum with a fast release, stabilized chewing gum. According to the method, a quantity of aspartame (APM) is mixed with an agglomerating agent, such as a modified cellulose, and a limited quantity of a solvent for the agglomerating agent, such as water. The quantity of solvent is limited so as to produce a mixture which is only moist or damp. This damp mixture is characterized as being dust-free, non-flowing and crumbly. The damp mixture is then dried and the dried mixture is comminuted, e.g. by grinding, to produce particles of APM ingredient with essentially a maximum particle size of about 0.017 inches. These particles of APM ingredient are then added to a chewing gum formulation.Type: GrantFiled: May 26, 1989Date of Patent: June 22, 1993Assignee: Firma Wilhelm Fette GmbHInventors: Steven F. Zibell, Mansukh M. Patel, Jayant C. Dave, Robert A. Payne
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Patent number: 5013786Abstract: Filler-containing thermoplastic molding materials having an improved surface and improved coatability contain, as essential components,(A) from 42 to 90% by weight of a thermoplastic polyamide,(B) from 9.5 to 55% by weight of fibrous or particulate fillers or mixtures of these and(C) from 0.5 to 3% by weight of a rubber impact modifier having reactive groups.Type: GrantFiled: February 10, 1989Date of Patent: May 7, 1991Assignee: Basf AktiengesellschaftInventors: Robert Payne, Walter Goetz, Uwe Wolf
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Patent number: 4148073Abstract: A high speed video display system suitable for use in operating video scoreboard displays is disclosed. Video data for a complete frame is converted from analogue to digital format and is directly loaded into a display memory (RAM). The digitized data is then outputted via a display interface to the display board which may consist of variable intensity devices, such as, incandescent light bulbs. The system, although under computer control, does not include the computer in the data handling path thereby permitting increased data handling rates. The video converter for the system includes circuits for changing the display format to produce "zoom" enlargements and wide screen displays suitable for racetrack applications.Type: GrantFiled: December 28, 1977Date of Patent: April 3, 1979Assignee: Stewart-Warner CorporationInventors: Gregory E. Slobodzian, Robert A. Payne, Wayne Fiedler
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Patent number: 4009335Abstract: A large display system capable of displaying a video image receives video signals, quantizes those signals to produce a digital code capable of representing variations in the light content of the image and processes the digital code so to control individual display devices on a large matrix of such devices to have different levels of visibility to thereby reproduce the video image for viewing by a large audience. A data processor is utilized to store the digital representation of the video image in memory so that on line or off line presentations can be made.Type: GrantFiled: August 9, 1973Date of Patent: February 22, 1977Assignee: Stewart-Warner CorporationInventors: Robert A. Payne, Gregory E. Slobodzian, Stanley A. Zielinski, Ralph M. Ravanesi