Abstract: A computer system includes a processor circuit, first and second memory systems, and a configurable memory assistance circuit. The processor circuit is used to run at least one application. The application issues a memory access operation. The configurable memory assistance circuit is in communication with the first and second memory systems and the processor circuit. The configurable memory assistance circuit accelerates the memory access operation for the application using data as the data is in transit between the first and second memory systems.

Abstract: Methods and apparatus relating to diagnostic testing of FPGAs for safety critical systems are described. In an embodiment, logic circuitry (e.g., a processor) performs one or more diagnostic operations on a portion of a Field Programmable Gate Array (FPGA) based on one or more test vectors. Memory stores the one or more test vectors. The logic circuitry performs the one or more diagnostic operations on the portion of the FPGA during runtime. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to diagnostic testing of FPGAs for safety critical systems are described. In an embodiment, logic circuitry (e.g., a processor) performs one or more diagnostic operations on a portion of a Field Programmable Gate Array (FPGA) based on one or more test vectors. Memory stores the one or more test vectors. The logic circuitry performs the one or more diagnostic operations on the portion of the FPGA during runtime. Other embodiments are also disclosed and claimed.

Abstract: A computer system includes a processor circuit, first and second memory systems, and a configurable memory assistance circuit. The processor circuit is used to run at least one application. The application issues a memory access operation. The configurable memory assistance circuit is in communication with the first and second memory systems and the processor circuit. The configurable memory assistance circuit accelerates the memory access operation for the application using data as the data is in transit between the first and second memory systems.

Abstract: A polyphase numerically controlled oscillator (PNCO) is defined to include a plurality of sub-numerically controller oscillators (SNCO's). Each SNCO is capable of receiving a clock signal at a first clock rate and an assigned phase offset signal. Each SNCO is configured to generate a digital waveform for the assigned phase offset signal. The PNCO also includes a plurality of frequency multipliers for generating a frequency multiplied representation of the digital waveform generated by each SNCO. The PNCO further includes a multiplexer configured to receive output from each of the frequency multipliers according to the first clock rate. The multiplexer is further configured to receive a select signal, wherein the select signal triggers the multiplexer at a second clock rate.