Abstract: A microprocessor that operates at the speed of the the bus or at a speed which is a multiple of the bus speed-on a selectable basis. The microprocessor includes a phase locked loop to generate clock signals for operations within the microprocessor and bus clock signals for data transfer operations on the bus. The present invention allows a microprocessor core to operate at the same frequency or twice the frequency of the address/data buses.

Abstract: A method and apparatus for powering down a microprocessor in a computer system. The method and apparatus includes a phase locked loop (PLL) circuit, wherein the phase locked loop generates bus clock signals for clocking the operations on the bus and core clock signals for clocking the core of the processor in response to global clock signal of the computer system. The microprocessor includes circuitry for processing data synchronous with the core clock signals. The method and circuit also includes circuitry for placing the processor in a reduced power consumption state in response to the execution of a power down instruction. In this manner, the computer system reduces power consumption.

Abstract: A microprocessor that operates at the speed of the the bus or at a speed which is a multiple of the bus speed on a selectable basis. The microprocessor includes a phase locked loop to generate clock signals for operations within the microprocessor and bus clock signals for data transfer operations on the bus. The present invention allows a microprocessor core to operate at the same frequency or twice the frequency of the address/data buses.

Abstract: A method and apparatus for allowing a processor to invalidate an individual line of its internal cache while in a non-clocked low power state. The present invention includes circuitry for placing the processor in a reduced power consumption state. The present invention also includes circuitry for powering up the processor out of the reduced power consumption state to invalidate data in the cache in order to maintain cache coherency while in the reduced power consumption state.

Abstract: A microprocessor that operates at the speed of the bus or at a speed which is a multiple of the bus speed on a selectable basis. The microprocessor includes a phase locked loop to generate clock signals to clock the operations within the microprocessor and bus clock signals to clock data transfer operations between the microprocessor and the bus.

Abstract: A method and apparatus for allowing a processor to invalidate an individual line of its internal cache while in a non-clocked low power state. The present invention includes circuitry for placing the processor in a reduced power consumption state. The present invention also includes circuitry for powering up the processor out of the reduced power consumption state to invalidate data in the cache in order to maintain cache coherency while in the reduced power consumption state.

Abstract: A complementary field effect transistor integrable voltage regulator suitable for use in CMOS integrated circuits includes first and second regulator sections coupled together. One regulator section includes a P channel MOSFET and an N channel MOSFET and a resistor, the P channel MOSFET and the resistor being coupled in series between an internal supply conductor and a reference conductor, the N channel MOSFET being connected in parallel therewith and having its gate electrode connected to the junction between the P channel MOSFET and the resistor. The gate electrode of the P channel MOSFET is connected to the output of another regulator, which includes a zener diode and a resistor coupled in series between the reference conductor and another voltage conductor.

Abstract: A very low current oscillator having a comparator and circuitry for providing a reference for the comparator is provided. A capacitor is coupled to one input of the comparator while the circuitry for providing a reference is coupled to another input of the comparator. A current source is used to charge the capacitor. The circuitry for providing a reference is capable of providing two different reference levels. A transistor to discharge the capacitor is coupled to the output of the comparator.

Abstract: Two P-channel MOS devices and two N-channel MOS devices are interconnected in a manner to provide a polarity reversal circuit. The circuit contains two input terminals and two output terminals. One of the output terminals is designated as a positive terminal while the other is designated as a negative terminal. Regardless of the polarity of voltage supplied to the input terminals, the positive voltage will always appear on the positive output terminal while the negative voltage will always appear on the negative output terminal.

Abstract: A complementary field effect transistor integrated circuit includes an input buffer, internal high density logic circuitry having a collapsed guard ring structure associated therewith, an internal power source which provides operating voltage for the internal high density logic lower than the junction reverse breakdown voltage of the collapsed guard ring structure, and an output level shifter circuit. The output level shifter circuit and input buffer, and internal power source have a conventional non-collapsed guard ring structure associated therewith.