Patents by Inventor Robert R. Leyendecker

Robert R. Leyendecker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230350823
    Abstract: An information handling system may include a management controller and a chassis having mounted therein at least one add-in card. The management controller may be configured to: retrieve connection information from the add-in card, the connection information indicating a physical location of the add-in card within the chassis; compare the connection information with expected connection information associated with the information handling system; determine that the physical location of the add-in card within the chassis is in conflict with a restriction associated with the add-in card; and transmit an error message based on the determining.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Applicant: Dell Products L.P.
    Inventors: Robert R. LEYENDECKER, Jun GU, Chien-Lin LEE, Jon Vernon FRANKLIN
  • Patent number: 11327916
    Abstract: In one embodiment, a method for enumerating logical identifiers for a plurality of backplanes of an information handling system includes: generating, by each of the plurality of backplanes, inventory information indicating a plurality of backplane attributes; sending, by each of the plurality of backplanes, the inventory information to a baseboard management controller; receiving, by the baseboard management controller, the inventory information from each of the plurality of backplanes; determining, by the baseboard management controller, a backplane topology of the information handling system based on the inventory information, the backplane topology indicating a backplane location for each of the plurality of backplanes; generating, by the baseboard management controller, a logical backplane identifier for each of the plurality of backplanes based on the backplane topology; and assigning, by the baseboard management controller, the logical backplane identifier to each of the plurality of backplanes.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: May 10, 2022
    Assignee: Dell Products L.P.
    Inventors: Robert R. Leyendecker, Kurt W. Shetler, Rui An
  • Patent number: 11157427
    Abstract: An information handling system may include a basic input/output system (BIOS), a management controller configured to provide out-of-band management of the information handling system, a plurality of communications bus root complex ports, and a storage backplane having a plurality of slots configured to receive respective storage resources. The information handling system may be configured to: store, at the management controller, an initial data structure containing a correspondence between the plurality of communications bus root complex ports and the plurality of slots; transmit, from the BIOS to the management controller, information regarding bus numbers for a plurality of enumerated information handling resources coupled to the communications bus; and determine, by the management controller, a correspondence between the bus numbers and the plurality of slots.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 26, 2021
    Assignee: Dell Products L.P.
    Inventors: Robert R. Leyendecker, Rui An
  • Publication number: 20210279193
    Abstract: An information handling system may include a basic input/output system (BIOS), a management controller configured to provide out-of-band management of the information handling system, a plurality of communications bus root complex ports, and a storage backplane having a plurality of slots configured to receive respective storage resources. The information handling system may be configured to: store, at the management controller, an initial data structure containing a correspondence between the plurality of communications bus root complex ports and the plurality of slots; transmit, from the BIOS to the management controller, information regarding bus numbers for a plurality of enumerated information handling resources coupled to the communications bus; and determine, by the management controller, a correspondence between the bus numbers and the plurality of slots.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 9, 2021
    Applicant: Dell Products L.P.
    Inventors: Robert R. LEYENDECKER, Rui AN
  • Publication number: 20200252280
    Abstract: An information handling system comprising may include a host system processor and a management controller communicatively coupled to the host system processor and configured to perform out-of-band management of the information handling system. The management controller may be further configured to, during boot of the information handling system read a known configuration for the information handling system from a storage resource accessible to the management controller, determine a current configuration of the information handling system, compare the known configuration to the current configuration, and in response to a mismatch between the known configuration and the current configuration, report an indication of the mismatch to a user of the information handling system and receive a desired user action for responding to the mismatch.
    Type: Application
    Filed: February 4, 2019
    Publication date: August 6, 2020
    Applicant: Dell Products L.P.
    Inventors: Timothy M. LAMBERT, Robert R. LEYENDECKER, Jordan CHIN, Peilin YAO
  • Patent number: 10534728
    Abstract: A method may include, in an information handling system comprising a processor and a management controller communicatively coupled to the processor and configured to provide management of the information handling system, executing by the management controller a management application for management of one or more storage resources of the information handling system, determining by the management controller whether one or more processor-attached storage resources are present in the information handling system, wherein the one or more processor-attached storage resources are coupled to the processor by other than a backplane of the information handling system, and responsive to determining that one or more processor-attached storage resources are present, executing by the management controller an adaptable virtual backplane that emulates a physical backplane to the management application as if the physical backplane were interfaced between the management application and the processor-attached storage resources.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: January 14, 2020
    Assignee: Dell Products L.P.
    Inventors: Chandrasekhar Mugunda, Yogesh P. Kulkarni, Balaji Bapu Gururaja Rao, Shivabasava Karibasa Komaranalli, Robert R. Leyendecker
  • Patent number: 10496560
    Abstract: An information handling system may include a processor; a plurality of connectors configured to receive a corresponding plurality of information handling resources, wherein each connector is located within a particular physical region of the information handling system and is communicatively coupled to the processor; and a management controller communicatively coupled to the processor and configured to provide out-of-band management of the information handling system. The management controller may be further configured to store a data structure that includes a mapping between respective ones of the physical regions and the connectors located within those physical regions; receive a command relating to a particular physical region; and based on the mapping in the data structure, transmit the command, via the connectors that are located in the particular physical region, to the information handling resources received by those connectors.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: December 3, 2019
    Assignee: Dell Products L.P.
    Inventors: Hasnain Shabbir, Robert R. Leyendecker
  • Publication number: 20190340139
    Abstract: An information handling system may include a processor; a plurality of connectors configured to receive a corresponding plurality of information handling resources, wherein each connector is located within a particular physical region of the information handling system and is communicatively coupled to the processor; and a management controller communicatively coupled to the processor and configured to provide out-of-band management of the information handling system. The management controller may be further configured to store a data structure that includes a mapping between respective ones of the physical regions and the connectors located within those physical regions; receive a command relating to a particular physical region; and based on the mapping in the data structure, transmit the command, via the connectors that are located in the particular physical region, to the information handling resources received by those connectors.
    Type: Application
    Filed: May 4, 2018
    Publication date: November 7, 2019
    Applicant: Dell Products L.P.
    Inventors: Hasnain SHABBIR, Robert R. LEYENDECKER
  • Publication number: 20190310951
    Abstract: A method may include, in an information handling system comprising a processor and a management controller communicatively coupled to the processor and configured to provide management of the information handling system, executing by the management controller a management application for management of one or more storage resources of the information handling system, determining by the management controller whether one or more processor-attached storage resources are present in the information handling system, wherein the one or more processor-attached storage resources are coupled to the processor by other than a backplane of the information handling system, and responsive to determining that one or more processor-attached storage resources are present, executing by the management controller an adaptable virtual backplane that emulates a physical backplane to the management application as if the physical backplane were interfaced between the management application and the processor-attached storage resources.
    Type: Application
    Filed: April 5, 2018
    Publication date: October 10, 2019
    Applicant: Dell Products L.P.
    Inventors: Chandrasekhar MUGUNDA, Yogesh P. KULKARNI, Balaji Bapu Gururaja RAO, Shivabasava Karibasa KOMARANALLI, Robert R. LEYENDECKER
  • Patent number: 7214883
    Abstract: The present invention provides an electrical cable having two or more conductors, one or more multistrip insulators separating the two or more conductors from one another, and a protective cover formed around the two or more conductors and one or more multistrip insulators. The multistrip insulator may include one or more dielectric strips, one or more protective strips or a combination thereof. The present invention also provides a method for manufacturing an electrical cable by providing two or more conductors, separating the two or more conductors from one another using one or more multistrip insulators, and forming a protective cover around the two or more conductors and one or more multistrip insulators.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: May 8, 2007
    Inventor: Robert R. Leyendecker
  • Patent number: 6466801
    Abstract: A circuit for use in a two-way pager of a paging system to transmit voice messages. The circuit includes: a microphone to receive an analog audio signal provided by a user; an analog-to-digital (A-D) converter coupled to the microphone; a memory; a processor coupled to the memory and to the A-D converter; and a transmitter coupled to the processor. The analog audio signals are typically voice messages spoken by the user, which the A-D converter samples and digitizes. The processor stores the digitized voice message in the memory. The user can then transmit the stored digitized voice message through the transmitter, which is processed through the paging system and provided to the intended recipient. In a further refinement, the circuit includes a playback circuit that allows the user to listen to the stored digitized voice message before transmitting the voice message to the rest of the paging system.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: October 15, 2002
    Assignee: Glenayre Electronics, Inc.
    Inventor: Robert R. Leyendecker
  • Publication number: 20020061774
    Abstract: A circuit for use in a two-way pager of a paging system to transmit voice messages. The circuit includes: a microphone to receive an analog audio signal provided by a user; an analog-to-digital (A-D) converter coupled to the microphone; a memory; a processor coupled to the memory and to the A-D converter; and a transmitter coupled to the processor. The analog audio signals are typically voice messages spoken by the user, which the A-D converter samples and digitizes. The processor stores the digitized voice message in the memory. The user can then transmit the stored digitized voice message through the transmitter, which is processed through the paging system and provided to the intended recipient. In a further refinement, the circuit includes a playback circuit that allows the user to listen to the stored digitized voice message before transmitting the voice message to the rest of the paging system.
    Type: Application
    Filed: September 23, 1996
    Publication date: May 23, 2002
    Applicant: GLENAYRE ELECTRONICS, INC.
    Inventor: ROBERT R. LEYENDECKER
  • Patent number: 5260613
    Abstract: A FFT buffer circuit having at least three FIFO buffers and a FIFO buffer lect circuit to separate incoming real-data into its in-phase and quadrature components and to output each component to a separate port for FFT, and also having a modified overflow detect circuit to automatically detect and eliminate overflow in the incoming real-data stream. In addition, the invention utilizes link hook-ups and receiver control signals for external control of both the automatic overflow reset and the data buffer timing.
    Type: Grant
    Filed: June 30, 1992
    Date of Patent: November 9, 1993
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Robert R. Leyendecker