Abstract: A programmable logic device is provided with phase-locked loop (“PLL”) circuitry that includes two serially connected PLL circuits. An input clock signal is processed by a first of the PLL circuits to produce an intermediate clock signal having a frequency different from the input clock signal frequency. The intermediate clock signal is processed by the second PLL circuit to produce a final modified clock signal having a frequency different from both the input clock signal frequency and the intermediate clock signal frequency. By providing two serially connected PLL circuits, each PLL circuit can be required to operate with frequencies in a narrower range than might otherwise be required in a single PLL circuit required to produce a given input-to-final frequency change. Other circuitry on the programmable logic device (e.g., input/output registers and programmable logic circuitry for processing data signals) is responsive to the input and final modified clock signals.

Abstract: A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.

Abstract: A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.

Abstract: An integrated circuit contains circuitry to operate in such a fashion to reduce output noise when switching output circuits from a programming mode to a user mode. In an implementation, the integrated circuit (125) is configurable in the programming mode with user configuration data. In the user mode, the integrated circuit will operate with the functionality as defined by the user during the programming mode. When switching from the programming mode to the user mode, each output (210) of the integrated circuit will switch to its user mode value. In order to minimize switching noise, the outputs are released to their user mode values not all at the same time.

Abstract: A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL” ) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.

Abstract: A programmable logic device is provided with phase-locked loop (“PLL”) circuitry that includes two serially connected PLL circuits. An input clock signal is processed by a first of the PLL circuits to produce an intermediate clock signal having a frequency different from the input clock signal frequency. The intermediate clock signal is processed by the second PLL circuit to produce a final modified clock signal having a frequency different from both the input clock signal frequency and the intermediate clock signal frequency. By providing two serially connected PLL circuits, each PLL circuit can be required to operate with frequencies in a narrower range than might otherwise be required in a single PLL circuit required to produce a given input-to-final frequency change. Other circuitry on the programmable logic device (e.g., input/output registers and programmable logic circuitry for processing data signals) is responsive to the input and final modified clock signals.

Abstract: A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides aL substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.

Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

Abstract: Apparatus and methods for configuring a plurality of programmable logic devices which include the steps of providing a source of configuration data and transferring the configuration data directly from the source to each of the programmable logic devices. In some embodiments, the methods permit the programmable logic devices to configure themselves without the intervention of an intelligent host such as a CPU, a microcontroller, or other types of intelligent logic. In other embodiments, configuration data files are used in conjunction with an intelligent host to configure the programmable logic devices. Configuration is performed at power-up or, alternatively, under user or software control.

Abstract: Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgement from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

Abstract: A digital data synchronizer, synchronizes a digital data system to an incoming serial bit stream having a segment of pseudo random bit sequence, which is a function of a predetermined primitive polynomial, preceeding the start of data. The synchronizer includes a first feedback shift register configured as a multiplier for generating the pseudo random bit sequence. The multiplier register operates on the incoming serial bit stream to determine whether a valid bit sequence of the primitive polynomial is present in the incoming serial bit stream, and if it is, a zero output is produced. A second feedback shift register configured as a divider produces a pseudo random bit sequence which is also a function of the predetermined primitive polynomial. A counter is provided to monitor the number of zeros outputted by the multiplier feedback shift register.