Abstract: An apparatus for controlling the transfer of data between a first remote processor constructed to process data words of a first length and a second remote processor constructed to process data words of a second length and which includes a storage member constructed to store data words of a third length. A DMA controller controls the transmission of data words between the storage member and the first remote processor. A first control processor controls the operation of a second processor and the DMA controller for transferring data from the second remote processor to the storage member. In response to instructions transmitted from the second remote processor, the first control processor will enable the second control processor to transfer data words of a third length to the storage member and will enable the DMA controller to transfer data words of the second length from the storage member to the second remote processor.

Abstract: A communication interface for controlling the transfer of data between a host processor configured to process data of a first length and a remote storage member configured to store data of a second length includes a bus controller for transferring data between the interface and the remote storage member, a data transfer member for controlling the transfer of data between the host processor and the interface, and a control processor for controlling operating of the bus controller and the transfer member. A first storage member stores data words of said second length and sequentially outputs the data words over a communication bus to the host processor configured to transmit data words of said first length. A second storage member stores data representing the operating status of the transfer member and the bus controller, enabling the control processor to monitor the status of the transfer member and the bus controller.

Abstract: A system for controlling the transfer of a data message over a common communication channel between a plurality of processing devices includes a MOS/LSI controller chip associated with each processing unit for constructing a message to be sent to a sending device acknowledging the receipt of the message and the validity of the message. Logic circuits are included which generate a predetermined sequence of two binary bits indicating the receipt of the message and the validity of the receiving message. The binary bits are framed by two other binary bits and the sequence repeated a predetermined number of times to construct an acknowledgment message. The controller chip further includes logic circuits for decoding the acknowledgment message.

Abstract: A system for controlling the flow of data over a common bus between a plurality of processing units is disclosed which preferably includes a MOS/LSI circuit controller chip associated with each processing unit for awarding priority of access to the common bus when two or more processing units attempt to simultaneously gain access to the common bus. A contention circuit located in each controller chip is responsive to the sensing of each bit in the address of its associated processing unit, and generates a plurality of transitions on the common bus during the time a binary one bit is sensed in the address and listens for the presence of any transition on the common bus during the time a binary zero is sensed in the address. Access to the common bus is lost when transitions are detected on the bus during the time a binary zero bit is sensed and acquired when no transitions have been detected at the completion of the sensing of the address of the requesting processing unit.

Abstract: A driving circuit arrangement for a gas-discharge display device operated asynchronously by a blanking signal generated in a processor applies a voltage level to each of the cells of the display device which is below the voltage level required to fire the cells upon the generation of the blanking signal. This arrangement enables the selected cells to fire upon the subsequent removal of the blanking signal. Switching members are operated by the generation of the blanking signal to precharge each of the cells in the display device during the blanking interval in which data transmitted from the processor selects the character to be displayed.