Abstract: Illustrative embodiments provide a reactivity control assembly for a nuclear fission reactor, a reactivity control system for a nuclear fission reactor having a fast neutron spectrum, a nuclear fission traveling wave reactor having a fast neutron spectrum, a method of controlling reactivity in a nuclear fission reactor having a fast neutron spectrum, methods of operating a nuclear fission traveling wave reactor having a fast neutron spectrum, a system for controlling reactivity in a nuclear fission reactor having a fast neutron spectrum, a method of determining an application of a controllably movable rod, a system for determining an application of a controllably movable rod, and a computer program product for determining an application of a controllably movable rod.

Abstract: Illustrative embodiments provide a reactivity control assembly for a nuclear fission reactor, a reactivity control system for a nuclear fission reactor having a fast neutron spectrum, a nuclear fission traveling wave reactor having a fast neutron spectrum, a method of controlling reactivity in a nuclear fission reactor having a fast neutron spectrum, methods of operating a nuclear fission traveling wave reactor having a fast neutron spectrum, a system for controlling reactivity in a nuclear fission reactor having a fast neutron spectrum, a method of determining an application of a controllably movable rod, a system for determining an application of a controllably movable rod, and a computer program product for determining an application of a controllably movable rod.

Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.

Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

Abstract: An apparatus is provided which tests the magnitude and sign digits of packed decimal binary numbers during performance of arithmetic operations which combine the numbers for the purpose of setting status bits used for setting condition codes, determining execution paths, setting the sign of the result and detecting invalid conditions.