Abstract: An example apparatus for writing a bit to a memory cell includes wordline driver circuitry configured to generate a first voltage in response to a row access enable signal. The apparatus also includes boost driver circuitry coupled to the wordline driver circuitry. The boost driver circuitry is configured to charge a capacitor using the first voltage and to generate a second voltage using the first voltage and a voltage at the capacitor in response to a boost enable signal. The apparatus also includes a wordline coupled to the memory cell and the wordline driver circuitry. The wordline is configured to output the first voltage or the second voltage to the memory cell.

Abstract: A method for storing data includes determining, using a first match line, that a match word satisfies a first content addressable memory (CAM) word stored in a CAM array, wherein the CAM array is configured to store a second CAM word that matches the first CAM word. The method further includes determining that a first parity bit associated with the first CAM word matches a first parity of the first CAM word. The method further includes, in response to determining that the first parity bit associated with the first CAM word matches the first parity determining, using the first match line, a first random access memory (RAM) word stored in a RAM array and outputting the first RAM word.

Abstract: A method for storing data includes determining, using a first match line, that a match word satisfies a first content addressable memory (CAM) word stored in a CAM array, wherein the CAM array is configured to store a second CAM word that matches the first CAM word. The method further includes determining that a first parity bit associated with the first CAM word matches a first parity of the first CAM word. The method further includes, in response to determining that the first parity bit associated with the first CAM word matches the first parity determining, using the first match line, a first random access memory (RAM) word stored in a RAM array and outputting the first RAM word.

Abstract: An example device includes a memory element configured to store a state for a bit in response to a write operation and to output an indication of the state for the bit in response to a read operation. The device includes first access circuitry coupled to the memory element. The first access circuitry is configured to allow a first current to flow through the first access circuitry in response to being driven in the read operation or the write operation. The device includes second access circuitry coupled to the memory element. The second access circuitry is configured to allow a second current to flow through the second access circuitry in response to being driven in the write operation. A transconductance of the first access device is different than a transconductance of the second access device.

Abstract: An example apparatus for writing a bit to a memory cell includes wordline driver circuitry configured to generate a first voltage in response to a row access enable signal. The apparatus also includes boost driver circuitry coupled to the wordline driver circuitry. The boost driver circuitry is configured to charge a capacitor using the first voltage and to generate a second voltage using the first voltage and a voltage at the capacitor in response to a boost enable signal. The apparatus also includes a wordline coupled to the memory cell and the wordline driver circuitry. The wordline is configured to output the first voltage or the second voltage to the memory cell.

Abstract: A circuit comprises a data storage element that includes a sampling stage configured to sample a data value, the sampling stage comprising a plurality of p-type devices, wherein at least one of the plurality of p-type devices is non-collinear relative to the other p-type devices, a plurality of n-type devices, wherein at least one of the plurality of n-type devices is non-collinear relative to the other n-type devices, a feedback stage configured to maintain the data value sampled by the sampling stage.

Abstract: A circuit comprises a data storage element that includes a sampling stage configured to sample a data value, the sampling stage comprising a plurality of p-type devices, wherein at least one of the plurality of p-type devices is non-collinear relative to the other p-type devices, a plurality of n-type devices, wherein at least one of the plurality of n-type devices is non-collinear relative to the other n-type devices, a feedback stage configured to maintain the data value sampled by the sampling stage.

Abstract: In some examples, a system, such as an integrated circuit device (IC), includes functional elements interspersed with access elements and associated test elements. The access elements and associated test elements may be used to determine a health status of the IC or an area of the IC. A health status determination can include, for example, identification of an area of the IC where performance may have degraded (e.g., has degraded or is about to degrade beyond desirable levels of performance). For example, a test element can be configured to generate a parametric output in response to an electrical stimulus, where the parametric output indicates a health status of one or more functional elements of the IC.

Abstract: In some examples, a system, such as an integrated circuit device (IC), includes functional elements interspersed with access elements and associated test elements. The access elements and associated test elements may be used to determine a health status of the IC or an area of the IC. A health status determination can include, for example, identification of an area of the IC where performance may have degraded (e.g., has degraded or is about to degrade beyond desirable levels of performance). For example, a test element can be configured to generate a parametric output in response to an electrical stimulus, where the parametric output indicates a health status of one or more functional elements of the IC.

Abstract: A system and method of conditioning differential clock signals iteratively adjusts the duty cycles and phases of the clock signals. The duty cycles of the clock signals are adjusted by comparing respective voltage corresponding to the duty cycles of respective clock signals in each of the differential pairs. The result of the comparison is used to adjust the duty cycles of the clock signal until the magnitudes of the voltages are substantially equal. The phases of the clock signals are adjusted by selecting two sets of two clock signals each that are assigned relative phases that differ from each other by the same amount. The selected sets of clock signals are processed so that the duty cycles of resulting signals correspond to the phases of the clock signals. The duty cycle of these signals is measured as described above and used to adjust the phases of the clock signals.

Abstract: A system and method of conditioning differential clock signals iteratively adjusts the duty cycles and phases of the clock signals. The duty cycles of the clock signals are adjusted by comparing respective voltage corresponding to the duty cycles of respective clock signals in each of the differential pairs. The result of the comparison is used to adjust the duty cycles of the clock signal until the magnitudes of the voltages are substantially equal. The phases of the clock signals are adjusted by selecting two sets of two clock signals each that are assigned relative phases that differ from each other by the same amount. The selected sets of clock signals are processed so that the duty cycles of resulting signals correspond to the phases of the clock signals. The duty cycle of these signals is measured as described above and used to adjust the phases of the clock signals.

Abstract: A differential pair of transistors includes a first transistor and a second transistor having their sources coupled together. Their sources are further coupled to ground via a pull-down network. A single-ended output is coupled to the drain of the second of the pair of differential transistors. A differential current adjust circuit is coupled to a drain of the first of the pair of differential transistors, and the current adjust circuit is configured so that the second side of the differential output driver circuit conducts approximately the same current as the first side of the differential output driver circuit.

Abstract: A differential pair of transistors includes a first transistor and a second transistor having their sources coupled together. Their sources are further coupled to ground via a pull-down network. A single-ended output is coupled to the drain of the second of the pair of differential transistors. A differential current adjust circuit is coupled to a drain of the first of the pair of differential transistors, and the current adjust circuit is configured so that the second side of the differential output driver circuit conducts approximately the same current as the first side of the differential output driver circuit.

Abstract: A differential pair of transistors includes a first transistor and a second transistor having their sources coupled together. Their sources are further coupled to ground via a pull-down network. A single-ended output is coupled to the drain of the second of the pair of differential transistors. A differential current adjust circuit is coupled to a drain of the first of the pair of differential transistors, and the current adjust circuit is configured so that the second side of the differential output driver circuit conducts approximately the same current as the first side of the differential output driver circuit.