Abstract: A method, remote answering machine controller and computer program product are provided for programmable control based upon message importance. Responsive to an incoming call being received, checking a current message priority is performed. Responsive to the identified current message priority, the incoming call is answered after a dynamically programmable number of incoming rings. Then a recorded message is delivered and a caller is prompted for selected priority. The caller selected priority is identified and stored with an incoming message for the incoming call. When the owner of the remote answering machine calls to collect messages, a current highest priority of the current messages is announced. The highest priority message of the current messages is played back first. Then the owner is prompted to continue with message play back.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: A method and apparatus are provided for providing a forgotten bolus warning for an insulin pump user. User selections for mealtimes are received and stored. A user selection for a warning wait period is received and stored. When a time past a mealtime plus the user selection for the warning wait period is identified, checking for a bolus having been taken is performed. Responsive to no bolus having been taken, the user is alerted with the forgotten bolus warning. The user is alerted with the forgotten bolus warning by an audible, visual, or tactile warning for a programmable period of time. The user selections for mealtimes are received and stored on a daily basis for each day of the week. The user selection for a warning wait period can be received and stored independently for each meal.

Abstract: A method and system for reducing a reflection coefficient below a predetermined value thereby reducing jitter by the variation of the effective impedance of a driver appearing to be bounded during state transitions. The driver may include a pull-up driver and a pull-down driver. In the pull-up driver, the transistors may be switched from a first state to a second state in a staggered fashion where the first state is complementary to the second state; In the pull-down driver, the transistors may be switched from a second state to a first state in a staggered fashion. By staggering the switching of the transistors in the pull-up driver and the pull-down driver, a portion of the current may flow from the pull-up driver to the pull-down driver thereby causing the variation of the effective impedance of the driver to appear to be bounded during state transitions.

Abstract: An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.

Abstract: A method and system for reducing a reflection coefficient below a predetermined value thereby reducing jitter by the variation of the effective impedance of a driver appearing to be bounded during state transitions. The driver may comprise a pull-up driver and a pull-down driver. In the pull-driver, the transistors may be switched from a first state to a second state in a staggered fashion where the first state is complementary to the second state. In the pull-down driver, the transistors may be switched from a second state to a first state in a staggered fashion. By staggering the switching of the transistors in the pull-up driver and the pull-down driver, a portion of the current may flow from the pull-up driver to the pull-down driver thereby causing the variation of the effective impedance of the driver to appear to be bounded during state transitions.

Abstract: The present invention provides a bus for use in a data processing system. In one embodiment, the bus includes a clock driver, a clock receiver, a plurality of drivers, and a plurality of receivers. The clock receiver is coupled to the clock driver by two clock bus lines carrying complementary clock pulses. Each of the plurality of receivers each coupled to a respective one of the plurality of drivers by bus lines, wherein the receivers detect signals on respective bus lines with respect to a reference voltage derived from a combination of the complementary clock pulses.

Abstract: A mixed voltage output driver includes an output sensing circuit that senses an output voltage at an output terminal and generates a voltage signal that corresponds to a voltage level at the output terminal. Next, an impedance selection circuit receives the voltage signal and generates a control signal in response to the output voltage having a higher logical uplevel than the mixed voltage output driver. The control signal is then received by an adjustable drive impedance circuit that is also coupled to an input terminal of the mixed voltage output driver and, in response thereto, the adjustable drive impedance circuit modifies an output drive impedance of the mixed voltage output driver. In another advantageous embodiment, the mixed voltage output driver only determines if the output voltage at the output terminal is at a logical uplevel before adjusting the output drive impedance.

Abstract: An active clamp circuit for digital circuits includes a first MOSFET serially connected between an upper power supply voltage and an input terminal to be clamped, and a second MOSFET serially connected between a lower voltage power supply and the input terminal. The voltages at the gates of the first and second MOSFETs are held at constant first and second reference voltages by a reference circuit and the first reference voltage at the gate of the first MOSFET is less than the second reference voltage at the gate of the second MOSFET. The first and second reference voltages can be changed by connecting the reference circuit to power supply voltages other than the power supply voltages to which the first and second MOSFETs are connected. The reference voltages can also be varied by adding stages of transistors which act as resistors in parallel to the reference circuit. When the first reference voltage is to be varied, it is recommended that the transistors of opposite type be biased independently.

Abstract: A driver for a signal line provides a desired pull-up voltage, different from a natural supply voltage, and desired terminating impedance. The driver forms a controllable split terminator voltage divider.

Abstract: Methods and apparatus are provided for implementing adjustable logic threshold in dynamic circuits. The dynamic circuit includes an intermediate precharge node. An output logic stage is connected to the intermediate precharge node. A threshold adjustment circuit is connected to the output logic stage. The threshold adjustment circuit receives a selection input to adjust a threshold of the output logic stage. The threshold adjustment circuit is formed of a first transistor and a second transistor coupled in parallel with a pair of series connected transistors included in the output logic stage. One or both of the first transistor and second transistor are selectively activated to adjust the threshold of the output logic stage.

Abstract: Methods and apparatus are provided for body control in silicon-on-insulator (SOI) domino circuits. The silicon-on-insulator (SOI) domino circuit includes a clock input and an input transistor stack including a plurality of input transistors. Each of the plurality of input transistors receives a data input. An intermediate precharge node is connected to the input transistor stack. An output inverter is connected to the intermediate precharge node. The output inverter includes a pair of silicon-on-insulator (SOI) transistors. A clocked transistor is connected to a body of at least one of the pair of silicon-on-insulator (SOI) transistors. The clocked transistor predischarges the body of the SOI transistor. Another clocked transistor is connected between ground and a body of an evaluate transistor connected to the input transistor stack. The body of the evaluate transistor is predischarged by the clocked transistor.

Abstract: A test device is formed on a chip which allows the susceptibility to failure of functional circuitry formed on the chip to be tested. The test device allows aggressive design of chips which include sensitive circuitry, such as precharged dynamic logic, by testing whether deviations from the design specification introduced during manufacturing of the chip are sufficient to cause failure of the functional circuitry.

Abstract: In brief, methods and apparatus are provided for bipolar elimination in silicon-on-insulator (SOI) domino circuits. Apparatus for bipolar elimination in silcon-on-insulator (SOI) domino circuit includes a domino silicon-on-insulator (SOI) field effect transistor. An input is coupled to the domino silicon-n-insulator (SOI) field effect transistor. A predischarging device is coupled to said domino silicon-on-insulator (SOI) field effect transistor. The predischarging device is activated during a precharge mode of the domino circuit, so that the SOI parasitic bipolar transistor is not activated. A dynamic input circuit couples the input to the domino silicon-on-insulator (SOI) field effect transistor. The output of the dynamic input circuit is low during the precharge mode. The output of the dynamic input circuit corresponds to the input during the evaluate mode. The output of the dynamic input circuit is used to gate the predischarging device.

Abstract: A test device is formed on a chip which allows the susceptibility to failure of functional circuitry formed on the chip to be tested. The test device allows aggressive design of chips which include sensitive circuitry, such as precharged dynamic logic, by testing whether deviations from the design specification introduced during manufacturing of the chip are sufficient to cause failure of the functional circuitry.

Abstract: A driver circuit for providing reduced AC defects includes an output driver transistor with an effective compensation resistor coupled to a control input of the output driver transistor. An input signal is coupled to the control input of the output driver transistor through the compensation resistor. A current sensing detector is coupled between the compensation resistor and the control input of the output driver transistor for detecting an AC defect responsive to an applied input signal. A field effect transistor can be used for the current sensing detector. Also a differential amplifier can be used for the current sensing detector for detecting smaller AC defects.

Abstract: A test device is formed on a chip which allows the susceptibility to failure of functional circuitry formed on the chip to be tested. The test device allows aggressive design of chips which include sensitive circuitry, such as precharged dynamic logic, by testing whether deviations from the design specification introduced during manufacturing of the chip are sufficient to cause failure of the functional circuitry.

Abstract: A control system for minimizing and controlling the current slew rate of an output device by using inductance to directly measure the current slew rate is provided. The control system may, for example, be used to control and minimize the current slew rate through signal drivers and allow for faster drivers and/or larger numbers of drivers on integrated circuit chips. In accordance with one embodiment of the invention, an inductor is serially coupled with an output device. A predriver is coupled to the gate of the output device for providing a voltage slew rate at the output device gate. A comparator is coupled to the inductor for sensing a voltage indicative of a current slew rate through the inductor and outputing a signal indicating whether the current slew rate exceeds or falls below a desired level.

Abstract: The present invention is a driver circuit for interfacing electronic components which have different supply voltages. The driver circuit includes a source terminal for receiving a source voltage, an output terminal connected to an off-chip electronic component, and a pull up circuit disposed between the source and output terminals for providing a field effect controlled current path between the source terminal and the output terminal. The pull up circuit includes a first transistor in series with a second transistor, the second transistor providing overvoltage stress relief for the first transistor.

Abstract: A single-chip programmable logic array (PLA) in which the AND (search) array outputs are coupled to the OR (readout) array through a NOT array of selectable on-chip inverters. Provision is also made for selectable interconnection of inverted or non-inverted NOT array outputs to each other.