Abstract: A system, method, and computer readable medium for context controlled data tapping utilizing parallel logic for integrated link monitoring including receiving a signal unit, indexing to a state associated with a current channel to determine a current context of the signal unit in parallel to host processing and assigning a bundle overhead associated with the signal unit.

Abstract: A system, method, and computer readable medium for time stamp offset in data packet bundling including filling a globally distributed time stamp based upon a globally distributed time, receiving a signal unit, resolving a difference in time between the globally distributed time stamp and the reception of the signal unit and assigning a time offset based upon the resolved time difference.

Abstract: System and method for compensating for DS0 timing source transients, such as may occur during a switchover to a new external reference, is described. In one embodiment, an SFI control signal is monitored for embedded frame position information. When the frame position information is initially detected, a 10-bit frame clock counter is reset to zero. The counter is then incremented using an 8.192 MHz clock. From that point on, each time the SFI frame position information is detected, the value of the frame clock counter is checked. If the counter value is zero, the counter continues to run freely. If the counter value is non-zero and the most significant bit (“MSB”) thereof is zero, the count of the frame clock counter is held for one clock period. If the counter value is non-zero and the MSB thereof is one, the count of the frame clock counter is advanced by a value of two, rather than one, for one clock period.

Abstract: The present invention provides an apparatus, system and method of increasing port availability for a communication switch. First, second and third M port crossbars are arranged to provide a crossbar with a increased number of ports available for the communication switch. K ports of a first M port crossbar are individually coupled to K ports of a second and a third M port crossbar via interconnect buses. Further, K ports of the second and third M port crossbars are individually coupled via interconnect buses resulting in L available ports on each the M port crossbars in which M>L>K.

Abstract: A technique for embedding a first clock phase within a second signal is described. In one embodiment, the invention comprises a method of embedding a phase of a first signal within a second signal comprising the steps of monitoring a first signal for a frame event, responsive to detection of a frame event in the first clock signal, determining a position of the frame event relative to a current segment of a second signal, and embedding in the current segment of the second signal a value representative of the relative position of the detected frame event.

Abstract: A system and method for optimizing state machine transitional performance in a high speed link (HSL) protocol stack at an application node disposed in a network. An input event decoder and a state decoder decode an input event and state-specific context information relating to a particular protocol layer involved in a layer service for a specific connection. The decoded state-specific context information is utilized for personalizing a generic state machine (GSM) logic structure in order to effectuate a layer-specific state logic package that is partitionable into a control plane and a data plane. The decoded input event is processed by the personalized state machine to generate encodable output event and next-state information. In parallel with the control plane operations, parametric tests and data operations with respect to the layer service are performed in the data plane, thereby improving state machine transitional processing in the application node.

Abstract: A system and method for introducing user-defined (e.g., proprietary) signals into a standard backplane. A front side backplane portion is provided with a set of connector holes that are electrically separated from corresponding connector holes provided on the backplane's rear side portion. Thus, whereas the separated front side connector portion is operable with standard bus signals, the rear side connector portion can support an independent signal pathway to carry one or more user-defined signals.

Abstract: A system and method for personalizing a generic state machine (GSM) logic structure in order to effectuate individual protocol layer functionality of a high speed link protocol stack at a network node (i.e., an application node) having a plurality of connections. An input event structure including at least a service access point (SAP) and a connection identifier (CID) associated with a select service provider layer is provided to a context switch and control block that is operable to retrieve latest state-specific context information based on the SAP and CID. The GSM logic structure is personalized based on the context information to effectuate appropriate service provider layer functionality. The input event is processed by the personalized GSM logic structure to generate next-state information and an output event vector including SAP/CID data for specifying appropriate destinations (i.e., one or more service user layers).

Abstract: A memory card cooperating with a network interface for receiving data entry and update signals from a database manager via a switch fabric and with a bus interface for outputting data on a system bus disposed in a system shelf, which shelf forms at least a portion of a telecommunications node having a distributed scalable database system. The memory card is operable to contain at least a portion of the distributed database in a high speed, high density memory block disposed thereon, which memory block is coupled to a network interface controller via a first memory interface and to a bus interface controller via a second memory interface. An arbiter is coupled to the first and second memory interfaces for arbitrating data input operations and data output operations with respect to the memory block.

Abstract: A signaling link interface (10) includes a high level data link controller (12) that receives signaling information from network elements in a telecommunication network. A link state controller (14) performs message transfer part level two processing on the signaling information. The link state controller (14) generates a response message that the high level data link controller (12) provides back to the network elements. The high level data link controller (12) and the link state controller (14) are implemented in hardware as field programmable gate array devices. Information related to operation of the signaling link interface (10) may be downloaded from a remote site into the field programmable gate array devices. The signaling link interface (10) processes signaling information received from a plurality of signaling links on a link by link basis.

Abstract: In particular embodiments, the present invention provides a system for managing signaling messages in a telecommunication system. The system includes a first control module that is operable to receive signaling messages from a plurality of signaling links, process the signaling messages, and send the processed signaling messages through a communication network interface. The system also includes a second control module that is operable to receive the signaling messages from the plurality of signaling links, process the signaling messages, and send the processed signaling messages through a communication network interface. The system further includes a Matelink coupled to the first control module and the second control module. The Matelink is operable to communicate the status of the first control module to the second control module and the status of the second control module to the first control module.

Abstract: In particular embodiments, the present invention provides an apparatus for controlling a signaling link. The apparatus includes a plurality of receivers and a plurality of drivers. Each receiver receives signaling messages from one of a plurality of first signaling links, and each driver sends signaling messages over one of a plurality of second signaling links. The apparatus also includes an interface that receives signaling messages and control data from a control module and sends signaling messages and control data to the control module. The apparatus further includes a processor coupled to the receivers, the drivers, and the interface. The processor receives signaling messages from the receivers and multiplexes portions of the signaling messages together for communication through the interface. The processor also receives portions of signaling messages from the interface and demultiplexes the portions for communication to the drivers.

Abstract: A bus control module for a delivery unit, which interfaces an optical fiber network to a switching matrix. The bus control module controls transport of control data and network data between various application modules of the delivery unit. The control data and network data are carried as datagrams on ingress links from the application modules and on egress links to the application modules.