Patents by Inventor Robert S. Pauley, Jr.

Robert S. Pauley, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10573354
    Abstract: Approaches, techniques, and mechanisms are disclosed for manufacturing and operating high density memory systems. The high density memory systems can increase the amount of memory available to a computing system by allowing the connection of multiple memory modules into a single memory interface on a motherboard via a memory adapter as described herein.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: February 25, 2020
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Satyanarayan Shivkumar Iyer, Robert S. Pauley, Jr.
  • Patent number: 9939855
    Abstract: A method of manufacture of an enhanced capacity memory system includes: providing a dual in-line memory module carrier having a memory module and an integrated memory buffer coupled to the memory module; coupling a memory expansion board, having a supplementary memory module, to the dual in-line memory module carrier including attaching a bridge transposer; and providing a system interface connector coupled to the integrated memory buffer and the bridge transposer for controlling the memory module, the supplementary memory module, or a combination thereof.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 10, 2018
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Victor Mahran, Robert S. Pauley, Jr.
  • Publication number: 20180081554
    Abstract: Approaches, techniques, and mechanisms are disclosed for manufacturing and operating high density memory systems. The high density memory systems can increase the amount of memory available to a computing system by allowing the connection of multiple memory modules into a single memory interface on a motherboard via a memory adapter as described herein.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 22, 2018
    Inventors: Satyanarayan Shivkumar Iyer, Robert S. Pauley, JR.
  • Patent number: 9648754
    Abstract: A system and method of manufacture of an integrated circuit device system includes: a module interposer having a module first side and a module second side; an outer chip assembly mounted to the module first side; a mirrored chip assembly mounted to the module second side, the mirrored chip assembly below the outer chip assembly; and a carrier attached to the module second side, the carrier includes a carrier first side and a carrier second side, the mirrored chip assembly suspended above the carrier first side.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 9, 2017
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Satyanarayan Shivkumar Iyer, Robert S. Pauley, Jr., Victor Mahran
  • Publication number: 20160070316
    Abstract: A method of manufacture of an enhanced capacity memory system includes: providing a dual in-line memory module carrier having a memory module and an integrated memory buffer coupled to the memory module; coupling a memory expansion board, having a supplementary memory module, to the dual in-line memory module carrier including attaching a bridge transposer; and providing a system interface connector coupled to the integrated memory buffer and the bridge transposer for controlling the memory module, the supplementary memory module, or a combination thereof.
    Type: Application
    Filed: November 16, 2015
    Publication date: March 10, 2016
    Inventors: Victor Mahran, Robert S. Pauley, JR.
  • Patent number: 9204550
    Abstract: A method of manufacture of an enhanced capacity memory system includes: providing a dual in-line memory module carrier having a memory module and an integrated memory buffer coupled to the memory module; coupling a memory expansion board, having a supplementary memory module, to the dual in-line memory module carrier including attaching a bridge transposer; and providing a system interface connector coupled to the integrated memory buffer and the bridge transposer for controlling the memory module, the supplementary memory module, or a combination thereof.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: December 1, 2015
    Assignee: SMART Modular Technologies, Inc.
    Inventors: Victor Mahran, Robert S. Pauley, Jr.
  • Patent number: 6930903
    Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: August 16, 2005
    Assignee: Netlist, Inc.
    Inventors: Jayesh R. Bhakta, Robert S. Pauley, Jr.
  • Patent number: 6930900
    Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: August 16, 2005
    Assignee: Netlist, Inc.
    Inventors: Jayesh R. Bhakta, Robert S. Pauley, Jr.
  • Patent number: 6873534
    Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: March 29, 2005
    Assignee: Netlist, Inc.
    Inventors: Jayesh R. Bhakta, Robert S. Pauley, Jr.
  • Patent number: 6751113
    Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: June 15, 2004
    Assignee: Netlist, Inc.
    Inventors: Jayesh R. Bhakta, Robert S. Pauley, Jr.